-
公开(公告)号:US20210167813A1
公开(公告)日:2021-06-03
申请号:US17171723
申请日:2021-02-09
Applicant: CISCO TECHNOLOGY, INC.
Inventor: Douglas Paul Arduini , Sung Kee Baek , Richard Anthony O'Brien , Joel Richard Goergen , Chad M. Jones , Jason DeWayne Potterf , Ruqi Li
Abstract: In one embodiment, a method includes receiving low voltage pulse power from power sourcing equipment at a powered device, synchronizing the powered device with a waveform of the low voltage pulse power received from the power sourcing equipment, and operating the powered device with high voltage pulse power received from the power sourcing equipment.
-
公开(公告)号:US20200309861A1
公开(公告)日:2020-10-01
申请号:US16901989
申请日:2020-06-15
Applicant: Cisco Technology, Inc.
Inventor: Xiqun Zhu , Sung Kee Baek , Robert Gregory Twiss
IPC: G01R31/42 , G01R19/165 , G01R31/50 , H02J3/00 , H02J13/00
Abstract: To reduce the rate at which a false alternating current (“AC”) loss alarming signal is generated, but at the same time detect an actual AC loss situation in a timely manner, the disclosed method describes an AC line power loss detection and active verification method. If the AC line input voltage dips momentarily lower than a standard sine wave amplitude, the AC line may not be considered lost as long as it still has energy to drive a load. The method inserts a momentary load across the AC line and compares the AC line voltage before and after the extra load is applied. If the AC power is present, this extra loading will increase the AC loading current momentarily, but will not affect the AC line voltage. However, if the AC power is lost, such loading will lower the AC line voltage, indicating a loss of power.
-
公开(公告)号:US20200153337A1
公开(公告)日:2020-05-14
申请号:US16191308
申请日:2018-11-14
Applicant: CISCO TECHNOLOGY, INC.
Inventor: Douglas Paul Arduini , Joel Richard Goergen , Sung Kee Baek
Abstract: In one embodiment, an apparatus includes a first stage comprising a first active switch, a first resonant inductor, and a resonant capacitor and a second stage comprising a second active switch, a second resonant inductor, and a filter capacitor. The first and second stages form a non-isolated multi-resonant converter for converting a DC input voltage to a DC output voltage.
-
公开(公告)号:US20200067305A1
公开(公告)日:2020-02-27
申请号:US16113655
申请日:2018-08-27
Applicant: CISCO TECHNOLOGY, INC.
Inventor: Xiqun Zhu , Sung Kee Baek
Abstract: In one embodiment, a hot swap inrush current limiter circuit includes a pair of paths connecting an input and a load, a first capacitor connected in series with a switch between the paths, a first resistor connected to one of the paths and to a junction between the switch and the first capacitor, a second capacitor connected in series with a second resistor between the paths, with a gate of the switch connected to a junction between the second capacitor and the second resistor, a first diode connected in parallel with the second capacitor, and a second diode connected in parallel with the second resistor to allow for discharge of the second capacitor when input power is off. A method is also disclosed herein.
-
公开(公告)号:US20200041579A1
公开(公告)日:2020-02-06
申请号:US16600361
申请日:2019-10-11
Applicant: Cisco Technology, Inc.
Inventor: Xiqun Zhu , Sung Kee Baek , Robert Gregory Twiss
IPC: G01R31/42 , G01R31/02 , G01R19/165 , H02J3/00 , H02J13/00
Abstract: To reduce the rate at which a false alternating current (“AC”) loss alarming signal is generated, but at the same time detect an actual AC loss situation in a timely manner, the disclosed method describes an AC line power loss detection and active verification method. If the AC line input voltage dips momentarily lower than a standard sine wave amplitude, the AC line may not be considered lost as long as it still has energy to drive a load. The method inserts a momentary load across the AC line and compares the AC line voltage before and after the extra load is applied. If the AC power is present, this extra loading will increase the AC loading current momentarily, but will not affect the AC line voltage. However, if the AC power is lost, such loading will lower the AC line voltage, indicating a loss of power.
-
公开(公告)号:US20170201122A1
公开(公告)日:2017-07-13
申请号:US15399765
申请日:2017-01-06
Applicant: Cisco Technology, Inc.
Inventor: Douglas P. Arduini , Sung Kee Baek , Richard Anthony O'Brien , John Beecroft , M. Baris Dogruoz
CPC classification number: H02J9/061 , H02M3/04 , H02M7/04 , H02M2001/007
Abstract: A power supply system may comprise a plurality of input buses and an output bus. A plurality of multi-input power supplies may be disposed between the plurality of input buses and the output bus. The plurality of multi-input power supplies may be configured to supply a predetermined amount of power to the output bus before and after a failure event. The failure event may comprise at least one of the following: a failure of a one of the plurality of multi-input power supplies and loss of power on one of the plurality of input buses. Each input to the power supply may include an independent power section to support near or full output power in the event of another input power loss. Any input line loss from an independent power bus/grid may provide line redundancy to the power supply and to the power system as an Uninterruptable Power Supply.
-
公开(公告)号:US09614365B2
公开(公告)日:2017-04-04
申请号:US14220905
申请日:2014-03-20
Applicant: Cisco Technology, Inc.
Inventor: Weizhong Tang , Sung Kee Baek , Craig Zimmerman
CPC classification number: H02H7/1213 , G06F1/26 , G06F11/16 , G06F11/2015 , H03K17/0822 , H04M19/08
Abstract: A system and method for preventing bus voltage sagging when an Oring-FET in an N+1 redundant power supply configuration is faulty during power up. Each redundant power supply includes an Oring-FET and a voltage comparator. The voltage comparator receives and compares an input voltage and an output voltage of the Oring-FET during power up. In the event input voltage is less than the output voltage, the Oring-FET is deemed to be operating properly and provides output to a communicatively coupled system bus in response to the input voltage reaching a predetermined voltage threshold level. In the event the input voltage is approximately equal to the output voltage, the voltage comparator assists in preventing inrush current from flowing from the communicatively coupled system bus and prevents voltage sagging on the communicatively coupled system bus when another redundant power supply configuration is providing power to the communicatively coupled system bus.
-
公开(公告)号:US20250097060A1
公开(公告)日:2025-03-20
申请号:US18961781
申请日:2024-11-27
Applicant: Cisco Technology, Inc.
Inventor: Chad M. Jones , Joel Richard Goergen , George Allan Zimmerman , Richard Anthony O'Brien , Douglas Paul Arduini , Jason DeWayne Potterf , Sung Kee Baek
Abstract: In one embodiment, a method includes transmitting pulse power on two wire pairs, the pulse power comprising a plurality of high voltage pulses with the high voltage pulses on the wire pairs offset between the wire pairs to provide continuous power, performing low voltage fault detection on each of the wire pairs between the high voltage pulses, and transmitting data on at least one of the wire pairs during transmittal of the high voltage pulses. Data transmittal is suspended during the low voltage fault detection.
-
公开(公告)号:US12126456B2
公开(公告)日:2024-10-22
申请号:US17560424
申请日:2021-12-23
Applicant: CISCO TECHNOLOGY, INC.
Inventor: Richard Anthony O′Brien , Douglas Paul Arduini , Sung Kee Baek , Ruqi Li , Joel Richard Goergen
IPC: H04L12/10 , G01R31/08 , G06F1/26 , H04L12/40 , H04L41/0677
CPC classification number: H04L12/10 , G01R31/085 , H04L41/0677 , G06F1/26 , G06F1/263 , G06F1/266 , H04L12/40045
Abstract: In one embodiment, an apparatus comprises an input power interface for receiving input power, a power control system for transmitting DC (Direct Current) pulse power on multiple phases over a cable to a plurality of powered devices and verifying cable operation during an off-time of pulses in the DC pulse power, and a cable interface for delivery of the DC pulse power on the multiple phases and data over the cable to the powered devices. A method for transmitting multiple phase pulse power is also disclosed herein.
-
公开(公告)号:US12126399B2
公开(公告)日:2024-10-22
申请号:US18187006
申请日:2023-03-21
Applicant: Cisco Technology, Inc.
Inventor: Douglas Paul Arduini , Ruqi Li , Chad M. Jones , Sung Kee Baek , Jason DeWayne Potterf , Joel Richard Goergen
CPC classification number: H04B3/54 , G01R31/083 , G01R31/50 , G05B9/02 , G06F1/305 , H02J13/00 , H02J13/00032 , H04L12/10 , H04L12/40045
Abstract: Techniques are provided for detecting a fault across a pair of lines. Pulse power is applied across the pair of lines. The pulse power comprises alternating pulse on-time intervals and pulse off-time intervals. During a pulse off-time interval, a resistor is connected across the pair of lines and then disconnected when a voltage across the pair of lines reaches a first droop percentage in a first period of time. After disconnecting the resistor, it is determined whether the voltage across the pair of lines droops at least a second droop percentage within a second period of time that begins after the first period of time. Occurrence of a line-to-line fault across the pair of lines is determined when the voltage across the pair of lines droops by at least the second droop percentage or more within the second period of time.
-
-
-
-
-
-
-
-
-