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公开(公告)号：US12272303B2
公开(公告)日：2025-04-08
申请号：US18294003
申请日：2023-05-23
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Mengqi Wang , Qi Wei , Wenbo Chen , Tiaomei Zhang , Sifei Ai , Cong Liu , Qian Xu
IPC: G09G3/3225
Abstract: The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N−1)th-level driving signal to obtain an Nth-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.
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公开(公告)号：US20250104640A1
公开(公告)日：2025-03-27
申请号：US18558393
申请日：2022-12-19
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Wenbo Chen , Mengqi Wang , Cong Liu , Qian Xu , Erjin Zhao
IPC: G09G3/3258
Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.
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公开(公告)号：US20250087166A1
公开(公告)日：2025-03-13
申请号：US18558383
申请日：2022-12-19
Inventor： Ziyang Yu , Haijun Qiu , Ming Hu , Zhiliang Jiang , Tianyi Cheng , Jianpeng Wu , Wenbo Chen , Mengqi Wang , Cong Liu , Qian Xu , Qingqing Yan , Pan Zhao , Qing He , Xiangnan Pan , Quanyong Gu
IPC: G09G3/3266 , G09G3/3258
Abstract: A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.
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公开(公告)号：US12161034B2
公开(公告)日：2024-12-03
申请号：US18448859
申请日：2023-08-11
Inventor： Yuanzhang Zhu , Ren Xiong , Qiang Tang , Guoqiang Wu , Fei Shang , Haijun Qiu
IPC: H10K59/131
Abstract: The present disclosure provides a display apparatus, a display panel of which includes a panel chip; a second bonding region of a main circuit board is provided with second display terminals coupled with first display terminals and second touch control terminals coupled with first touch control terminals; each of segment touch control lines includes a first segment coupled between one second touch control terminal and one main connector in a first region, and a second segment coupled between a touch control chip and one main connector in a second region; a third region and a fourth region of a jumper connection circuit board are bonded with the first region and the second region respectively; the segment touch control lines are in one-to-one correspondence with jumper connection lines, each jumper connection line is coupled between one jumper connector in the third region and one jumper connector in the fourth region.
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45.发明授权公开(公告)号：US11706965B2
公开(公告)日：2023-07-18
申请号：US17650374
申请日：2022-02-08
Inventor： Haijun Qiu , Yangpeng Wang , Benlian Wang , Haijun Yin , Yang Wang , Yao Hu , Weinan Dai
CPC classification number: H10K59/353 , H10K59/352 , H10K71/00 , H10K71/164 , H10K71/166
Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, all being not overlapped but being spaced apart. The third sub-pixels have a first symmetry axis and a second symmetry axis that are perpendicular to each other. The first symmetry axis extends through a geometric center of a respective first sub-pixel adjacent to a respective third sub-pixel of the plurality of third sub-pixels, intersects a first edge of the respective third sub-pixel at a first intersection point, and intersects a second edge of the adjacent respective first sub-pixel at a second intersection point. A distance between the first intersection point and the second intersection point is a minimum distance between the respective third sub-pixel and the respective first sub-pixel. The second symmetry axis is similarly configured with respect to a respective second sub-pixel and the respective third sub-pixel.
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Patent Agency Ranking
46.发明授权公开(公告)号：US11271048B2
公开(公告)日：2022-03-08
申请号：US16469110
申请日：2018-11-14
Inventor： Haijun Qiu , Yangpeng Wang , Benlian Wang , Haijun Yin , Yang Wang , Yao Hu , Weinan Dai
Abstract: A pixel arrangement structure, an organic electroluminescent display panel, a metal mask, a display device are provided, the pixel arrangement structure including: first sub-pixels, second sub-pixels and third sub-pixels, all being not overlapped but being spaced apart; one first sub-pixels functions as a central point and other four first sub-pixels function as four vertices to define a first virtual rectangle comprising four second virtual rectangles in a 2×2 matrix in mirror symmetry; the second sub-pixels are at central points of side edges of the first virtual rectangle; two second sub-pixels at central positions of two adjacent side edges of the first virtual rectangle, one first sub-pixel at a vertice of the first virtual rectangle where the two adjacent side edges intersect, and another first sub-pixels at the central point of the first virtual rectangle define four vertices of each second virtual rectangle; the third sub-pixels are within the second virtual rectangles and each is shaped as: a concave polygon, or a closed pattern formed by continuous lines comprising curved lines.
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公开(公告)号：US11251231B2
公开(公告)日：2022-02-15
申请号：US16477515
申请日：2018-12-17
Inventor： Weinan Dai , Yang Wang , Yangpeng Wang , Benlian Wang , Haijun Yin , Haijun Qiu , Yao Hu
IPC: H01L27/32
Abstract: A pixel arrangement structure, an organic light emitting diode display panel, a display device and a mask plate assembly are disclosed in the disclosure. The pixel arrangement structure includes a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels. The positions of the sub-pixels are not overlapped with each other. One of the plurality of first sub-pixels is located at the center position of a first virtual rectangle. Four of the plurality of first sub-pixels are located at four vertex angle positions of the first virtual rectangle, respectively. Four of the plurality of second sub-pixels are located at the center positions of four sides of the first virtual rectangle, respectively. The first virtual rectangle is divided into four second virtual rectangles, and the inside of each of the four second virtual rectangles comprises one third sub-pixel of the plurality of third sub-pixels.
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公开(公告)号：US10401664B2
公开(公告)日：2019-09-03
申请号：US14800987
申请日：2015-07-16
Inventor： Sijun Lei , Liang Gao , Hang Min , Fei Shang , Haijun Qiu
IPC: G02F1/1333 , G02F1/133
Abstract: The embodiment of the invention relates to the field of display technology, and provides a curved surface display device whose curvature can be adjusted flexibly after assembly. The curved surface display device may comprise a liquid crystal display module, and may also comprise at least one adjustment frame, each adjustment frame comprises a first portion and a second portion, both of the first portion and the second portion comprise a fixed end and a movable end, the fixed end of the first portion and the fixed end of the second portion are respectively attached to the two edges of the liquid crystal display module that are perpendicular to the horizontal direction in case of being viewed normally; an adjustment distance is present between the movable end of the first portion and the movable end of the second portion, the adjustment frame is provided with an adjustment screw which movably connects the movable end of the first portion and the movable end of the second portion; the adjustment frame is used for changing the size of the adjustment distance by regulating the adjustment screw, so as to vary the curvature of the liquid crystal display module. Embodiments of the invention may be used for manufacturing the curved surface display device.
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49.发明申请公开(公告)号：US20180331126A1
公开(公告)日：2018-11-15
申请号：US15578534
申请日：2016-11-02
Inventor： Zhuo Xu , Yajie Bai , Xiaolin Wang , Rui Wang , Fei Shang , Haijun Qiu
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1225 , H01L21/707 , H01L27/1214 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1262 , H01L27/127 , H01L27/1288 , H01L27/3248 , H01L27/326 , H01L27/3262 , H01L27/3276 , H01L29/78633 , H01L29/7869
Abstract: The present a plication discloses an array substrate, a display panel a splay apparatus having the same, and a fabricating method thereof The array substrate includes a base substrate; a first electrode and a second electrode, the first electrode and the second electrode being two different electrodes selected from a pixel electrode and a common electrode; and a thin film transistor including an active layer, an etch stop layer on a side of the active layer distal to the base substrate, a first node, and a second node.
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公开(公告)号：US09966444B2
公开(公告)日：2018-05-08
申请号：US14801445
申请日：2015-07-16
Inventor： Wu Wang , Haijun Qiu , Fei Shang , Guolei Wang
IPC: H01L29/417 , G02F1/1362 , H01L29/786 , G02F1/1368
CPC classification number: H01L29/41733 , G02F1/1362 , H01L29/786
Abstract: Disclosed is a thin film transistor, including a gate electrode, a source electrode and a drain electrode. The source electrode includes a loop structure with an opening, and a width of the opening is less than a maximum width of an inner ring of the loop structure of the source electrode in a direction identical to a direction of the width of the opening. The drain electrode is surrounded by the loop structure, and is not in contact with the source electrode. The drain electrode is distant from the inner ring of the loop structure of the source electrode at a same interval.
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