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    SENSOR INTEGRATED CIRCUIT WITH INTEGRATED COIL
    42.
    发明申请
    SENSOR INTEGRATED CIRCUIT WITH INTEGRATED COIL 有权

    公开(公告)号：US20220310853A1

    公开(公告)日：2022-09-29

    申请号：US17806758

    申请日：2022-06-14

    Applicant: Allegro MicroSystems, LLC

    Inventor： Ravi Vig ,  William P. Taylor ,  Paul A. David ,  P. Karl Scheller ,  Andreas P. Friedrich

    IPC: H01L29/82 ,  G01R33/06 ,  G01R33/00 ,  G01D5/14

    Abstract: A sensor includes a lead frame having a first surface, a second opposing surface, and a plurality of leads and a semiconductor die having a first surface attached to the first surface of the lead frame and a second, opposing surface. The sensor further includes a non-conductive mold material enclosing the die and at least a portion of the lead frame, a conductive coil secured to the non-conductive mold material, a mold material secured to the non-conductive mold material and enclosing the conductive coil, wherein the mold material has a central region and an element disposed in the central region of the mold material.

    Photodetector with a buried layer
    43.
    发明授权
    Photodetector with a buried layer 有权

    公开(公告)号：US11296247B2

    公开(公告)日：2022-04-05

    申请号：US16272005

    申请日：2019-02-11

    Applicant: Allegro MicroSystems, LLC

    Inventor： Bryan Cadugan ,  Harianto Wong ,  William P. Taylor

    IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/105

    Abstract: An electronics module assembly for detecting photons is provided to include: a substrate layer; a buried layer deposited upon a first surface area of the substrate layer; an intrinsic layer deposited upon a first portion of a first surface area of the buried layer; a plug layer deposited upon a second portion of the first surface area of the buried layer; a p-plus layer deposited upon a first surface area of the intrinsic layer; an n-plus layer deposited upon a first surface area of the plug layer; a pre-metal dielectric (PMD) layer deposited upon the p-plus layer and n-plus layer; a first node coupled, through the PMD layer, to the p-plus layer; and a second node coupled, through the PMD layer, to the n-plus layer.

    Magnetic field sensor and method having reduced false switching
    45.
    发明授权
    Magnetic field sensor and method having reduced false switching 有权

    公开(公告)号：US10976183B2

    公开(公告)日：2021-04-13

    申请号：US16522810

    申请日：2019-07-26

    Applicant: Allegro MicroSystems, LLC

    Inventor： Paul A. David ,  William P. Taylor

    IPC: G01D5/244

    Abstract: A magnetic field sensor includes a substrate first and second magnetic field sensing elements, comprising first and second magnetoresistance elements, respectively. The first and second magnetic field sensing elements are responsive to the magnet. At or more positions of the magnet relative to the first and second magnetic field sensing elements while the magnet is stopped moving, at least one of the first magnetic field sensing element or the second magnetic field sensing element is in saturation in response to the magnet. The magnetic field sensor also includes a third magnetic field sensing element proximate to the first and second magnetoresistance elements, the third magnetic field sensing element operable to generate a third magnetic field sensing element signal responsive to the magnet, wherein, at the one or more positions while the magnet is stopped moving, the third magnetic field sensing element is not in saturation in response to the magnet or saturates at a higher magnetic field than the first and second magnetic field sensing elements in response to the magnet.

    PHOTODETECTOR WITH A BURIED LAYER
    46.
    发明申请
    PHOTODETECTOR WITH A BURIED LAYER 审中-公开

    公开(公告)号：US20200259033A1

    公开(公告)日：2020-08-13

    申请号：US16740816

    申请日：2020-01-13

    Applicant: Allegro MicroSystems, LLC

    Inventor： Bryan Cadugan ,  Harianto Wong ,  William P. Taylor

    IPC: H01L31/102 ,  H01L31/0224 ,  H01L31/18

    Abstract: According to an embodiment of the present disclosure, a photodetector device can include a substrate layer; a bottom contacting layer disposed over a surface of the substrate layer and having a first contacting region and a second contacting region, the bottom contacting layer providing a low resistance path between the first and second contacting regions; an insulating layer disposed over a surface of the bottom contacting layer; an intrinsic region disposed within the insulating layer, the intrinsic region in electrical contact with the first contacting region of the bottom contacting layer, the intrinsic region comprising a low band-gap material; a metal contact disposed within the insulating layer and in electrical contact with the second contacting region of the bottom contacting layer; an anode in electrical contact with the intrinsic region; and a cathode in electrical contact with the metal contact.

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