Time synchronization method in wireless sensor network
    41.
    发明授权
    Time synchronization method in wireless sensor network 有权
    无线传感器网络中的时间同步方法

    公开(公告)号:US08571008B2

    公开(公告)日:2013-10-29

    申请号:US12743310

    申请日:2008-06-12

    IPC分类号: H04J3/06

    摘要: The present invention relates to a time synchronization method in a wireless sensor network. In the present invention, if an upper node requests a lower reference node to start time synchronization, the lower reference node broadcasts a first sync reference packet. The upper node receives the first sync reference packet and transmits the first sync reference packet reception time to the lower reference node. The lower reference node broadcasts the first sync reference packet reception time, such that the other nodes perform time synchronization on the basis of the first sync reference packet reception time. Meanwhile, the lower reference node estimates the first sync reference packet reception time of the upper node to calculate the reception estimation time, and transmits the reception estimation time to a determination node that is two hops anterior to the lower reference node. Therefore, the determination node compares the reception time received from the upper node and the reception estimation time received from the lower reference node and determines whether a capture attack on the upper node has occurred.

    摘要翻译: 本发明涉及无线传感器网络中的时间同步方法。 在本发明中,如果上层节点请求较低参考节点开始时间同步,则下参考节点广播第一同步参考分组。 上级节点接收第一同步参考分组,并将第一同步参考分组接收时间发送到下参考节点。 下参考节点广播第一同步参考分组接收时间,使得其他节点基于第一同步参考分组接收时间执行时间同步。 同时,下参考节点估计上级节点的第一同步参考分组接收时间以计算接收估计时间,并且将接收估计时间发送到作为下参考节点之前的两跳的确定节点。 因此,确定节点比较从上层节点接收到的接收时间和从较低参考节点接收的接收估计时间,并确定是否发生了对上层节点的捕获攻击。

    Intelligent parking guidance apparatus and method
    42.
    发明授权
    Intelligent parking guidance apparatus and method 有权
    智能停车引导装置及方法

    公开(公告)号:US07825827B2

    公开(公告)日:2010-11-02

    申请号:US11929830

    申请日:2007-10-30

    IPC分类号: B60Q1/48

    CPC分类号: G08G1/14 G08G1/017

    摘要: Provided are an intelligent parking guidance apparatus and method. The intelligent parking guidance apparatus includes: an image sensor node recognizing a vehicle number of a vehicle, sensor nodes determining whether the vehicle exists in their own positions, a parking management server generating information for guiding the vehicle to an available parking space, and a mobile communication terminal receiving the information. The intelligent parking guidance apparatus and method provide information regarding parking lots which are within a predetermined distance from a destination and available parking spaces of each parking lot, to a driver, as well as provide a road guidance service to the driver to guide his/her vehicle to the destination, so that the driver can select an optimal parking lot. Also, when the vehicle enters the parking lot, the intelligent parking guidance apparatus and method guide the driver to an available empty parking space, thereby reducing difficulties in finding a parking space in a place which is unfamiliar to the driver.

    摘要翻译: 提供了一种智能停车引导装置和方法。 智能停车引导装置包括:识别车辆的车辆编号的图像传感器节点,确定车辆是否存在于其自己的位置的传感器节点,产生用于将车辆引导到可用停车位的信息的停车管理服务器,以及移动 通信终端接收信息。 智能停车引导装置和方法提供关于从目的地预定距离内的停车场以及每个停车场的可用停车位到驾驶员的信息,以及向司机提供道路指导服务以指导他/她 车辆到目的地,以便驾驶员可以选择最佳的停车场。 此外,当车辆进入停车场时,智能停车引导装置和方法将驾驶员引导到可用的空闲停车位,从而减少在驾驶员不熟悉的地方找到停车空间的困难。

    TEST HANDLER, METHOD FOR LOADING AND MANUFACTURING PACKAGED CHIPS, AND METHOD FOR TRANSFERRING TEST TRAYS
    44.
    发明申请
    TEST HANDLER, METHOD FOR LOADING AND MANUFACTURING PACKAGED CHIPS, AND METHOD FOR TRANSFERRING TEST TRAYS 有权
    测试处理器,装载和制造包装夹具的方法以及传送测试托盘的方法

    公开(公告)号:US20090167294A1

    公开(公告)日:2009-07-02

    申请号:US12339785

    申请日:2008-12-19

    IPC分类号: G01R31/26

    CPC分类号: G01R31/2893

    摘要: A test handler, a packaged chip loading method, a test tray transferring method, and a packaged chip manufacturing method are provided. The test handler may include a loading unit, a chamber system, an unloading unit, at least one rotating unit and a transferring unit. The loading unit may include a loading buffer disposed to be movable along a moving path formed over a loading position and a loading picker to perform a loading process on the test tray located at the loading position. The chamber system having the packaged chips connected to a hi-fix board and tested. The unloading unit may include an unloading picker to perform an unloading process on the test tray located at an unloading position. The at least one rotating unit may be disposed between the loading unit and the unloading unit to rotate the test tray transferred from the loading unit from a horizontal posture to a vertical posture, and to rotate the test tray transferred from the chamber system from a vertical posture to a horizontal posture. The transferring unit may transfer the test tray.

    摘要翻译: 提供了测试处理器,封装芯片加载方法,测试托盘传送方法和封装芯片制造方法。 测试处理器可以包括加载单元,室系统,卸载单元,至少一个旋转单元和传送单元。 装载单元可以包括装载缓冲器,其设置成沿着装载位置上形成的移动路径可移动,并且装载拾取器可在位于装载位置处的测试盘上执行装载过程。 该室系统具有连接到Hi-fix板并被测试的封装芯片。 卸载单元可以包括卸载拾取器,以在位于卸载位置的测试盘上执行卸载过程。 所述至少一个旋转单元可以设置在所述装载单元和所述卸载单元之间,以将从所述装载单元传送的所述测试托盘从水平姿态旋转到垂直姿势,并且将从所述室系统传送的所述测试托盘从竖直 姿势为水平姿势。 传送单元可以传送测试托盘。

    Methods of fabricating integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region
    45.
    发明授权
    Methods of fabricating integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region 有权
    制造集成电路的方法包括在栅极电极和源极/漏极区域之间延伸的金属硅化物触点

    公开(公告)号:US06169020A

    公开(公告)日:2001-01-02

    申请号:US09137598

    申请日:1998-08-21

    IPC分类号: H01L2120

    CPC分类号: H01L21/76895 Y10S257/90

    摘要: The presence and absence of sidewall spacers are used to provide discontinuous and continuous contacts respectively, between a gate electrode and a source/drain region. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit substrate. A source/drain region is formed in the integrated circuit substrate therebetween. The first electrode includes a first sidewall spacer on a first sidewall thereof facing the second gate electrode. The second gate electrode is free of (i.e. does not include) a sidewall spacer on a second sidewall thereof facing the first electrode. A metal silicide layer is formed on the first gate electrode, on the second gate electrode and extending from the second gate electrode onto the second sidewall and onto the source/drain region. The first sidewall spacer is free of the metal silicide layer thereon. The metal suicide layer is preferably formed by forming a metal layer on the first gate electrode, on the first sidewall spacer, on the source/drain region, on the second sidewall and on the second gate electrode. The metal layer is reacted with the first gate electrode, the source/drain region, the second sidewall and the second gate layer, to thereby form the metal silicide layer on the first gate electrode, on the second gate electrode and extending from the second gate electrode onto the second sidewall and onto the source/drain region. The metal layer is then removed from the first sidewall spacer.

    摘要翻译: 侧壁间隔物的存在和不存在分别用于在栅极电极和源极/漏极区域之间提供不连续和连续的触点。 特别地,第一和第二间隔开的栅电极形成在集成电路基板上。 源极/漏极区域形成在其间的集成电路基板中。 第一电极包括在其面向第二栅电极的第一侧壁上的第一侧壁间隔物。 第二栅极电极在其面向第一电极的第二侧壁上没有(即不包括)侧壁间隔物。 金属硅化物层形成在第一栅电极上,在第二栅电极上并且从第二栅电极延伸到第二侧壁上并且在源/漏区上延伸。 第一侧壁间隔物上没有金属硅化物层。 金属硅化物层优选通过在第一侧壁间隔,第一侧壁间隔物,源极/漏极区域,第二侧壁和第二栅电极上形成金属层而形成。 金属层与第一栅极电极,源极/漏极区域,第二侧壁和第二栅极层反应,从而在第一栅电极上,在第二栅电极上形成金属硅化物层,并从第二栅极延伸 电极到第二侧壁上并且到达源极/漏极区域。 然后从第一侧壁间隔物去除金属层。

    Semiconductor device and a method of manufacture
    46.
    发明授权
    Semiconductor device and a method of manufacture 失效
    半导体器件及其制造方法

    公开(公告)号:US5965939A

    公开(公告)日:1999-10-12

    申请号:US838044

    申请日:1997-04-22

    摘要: A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

    摘要翻译: 提供一种半导体器件,其具有闭合台阶部分和包括在全局台阶部分上具有平坦化表面的绝缘层的全局阶跃部分。 通过在全局台阶部分上形成绝缘层,然后通过光刻工艺进行图案化,形成虚拟图案。 在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后,在封闭台阶部分和全局台阶部分上形成BPSG层,然后BPSG层被热封, 处理以使其回流。 作为具有平坦化表面的绝缘中间层的BPSG层。 改进的平面化减少了随后的金属化处理中的开槽和不连续的发生,从而提高了半导体器件的产量和电特性。