公开(公告)号：US6148367A

公开(公告)日：2000-11-14

申请号：US777966

申请日：1996-12-24

申请人： Toshiaki Tsuboi ,  Akira Yamamoto ,  Shigeo Honma ,  Yoshihiro Asaka ,  Koji Ozawa ,  Hiroyuki Kitajima ,  Michio Miyazaki

发明人： Toshiaki Tsuboi ,  Akira Yamamoto ,  Shigeo Honma ,  Yoshihiro Asaka ,  Koji Ozawa ,  Hiroyuki Kitajima ,  Michio Miyazaki

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC分类号： G06F12/0873 ,  G06F12/0866 ,  G06F12/0804 ,  G06F2212/312

摘要： In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.

摘要翻译： 在向每个存储单元分配高速缓冲存储器的区域时，对每个存储单元进行高速缓冲存储器的适当分配。 如果写入数据量等于或大于阈值，则对每个盘单元设置分配限制。 如果CPU发出数据写请求，要求数据量等于或大于分配限制，则数据写入请求将保持在等待状态，直到写入数据量小于分配限制为止。 因此，对于盘单元的分配量既不太大也不太小。 以这种方式，可以实现对每个盘单元的高速缓冲存储器的适当分配。

公开(公告)号：US5917999A

公开(公告)日：1999-06-29

申请号：US877627

申请日：1997-06-18

申请人： Akira Yamamoto ,  Hiroyuki Kitajima ,  Kouji Arai ,  Yoshihisa Kamo

发明人： Akira Yamamoto ,  Hiroyuki Kitajima ,  Kouji Arai ,  Yoshihisa Kamo

IPC分类号： G06F3/06 ,  G06F11/10 ,  G06F12/08 ,  G06F12/16 ,  G06F13/10 ,  G11C29/00

CPC分类号： G06F11/1076 ,  G06F2211/1009

摘要： When receiving a write request from a processor, a control unit checks the condition of existence (or the presence/absence) in a cache for information necessary for generation of an updated value of a parity record, receives write data and reports the completion of the write request to the processor. In asynchronism with the write request from the processor, the control unit performs a load process for that information among the information necessary for generation of the updated value of the parity record which may be prepared in asynchronism with the write request from the processor and a write after process for the updated value of the parity record.

公开(公告)号：US5835938A

公开(公告)日：1998-11-10

申请号：US868075

申请日：1997-06-03

申请人： Akira Yamamoto ,  Takao Satoh ,  Shigeo Honma ,  Yoshihiro Asaka ,  Yoshiaki Kuwahara ,  Hiroyuki Kitajima

发明人： Akira Yamamoto ,  Takao Satoh ,  Shigeo Honma ,  Yoshihiro Asaka ,  Yoshiaki Kuwahara ,  Hiroyuki Kitajima

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F12/00 ,  G06F12/08 ,  G06F13/16

CPC分类号： G06F12/0866 ,  G06F11/2007 ,  G06F11/2087 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0689 ,  G06F11/2005 ,  G06F11/2089 ,  G06F12/0804 ,  G06F2206/1012

摘要： For a write request from the CPU, the control unit selects a specific disk unit in the disk unit group for the immediate writing of data. In a second kind of load distribution a disk unit is selected to execute read and staging other than the above-mentioned specific disk.

摘要翻译： 对于来自CPU的写请求，控制单元选择磁盘单元组中的特定磁盘单元以立即写入数据。 在第二种负载分配中，选择磁盘单元来执行除上述特定磁盘之外的读取和分段。

公开(公告)号：US5261065A

公开(公告)日：1993-11-09

申请号：US491235

申请日：1990-03-09

申请人： Shoo Urabe ,  Masashi Tsuchida ,  Hideo Mutoh ,  Yukio Nakano ,  Toshio Honma ,  Kiyoshi Yata ,  Hiroyuki Kitajima ,  Tadashi Ohsone ,  Nobuhiro Taniquchi

发明人： Shoo Urabe ,  Masashi Tsuchida ,  Hideo Mutoh ,  Yukio Nakano ,  Toshio Honma ,  Kiyoshi Yata ,  Hiroyuki Kitajima ,  Tadashi Ohsone ,  Nobuhiro Taniquchi

IPC分类号： G06F12/00 ,  G06F17/30 ,  G06F15/40

CPC分类号： G06F17/30477 ,  Y10S707/99931

摘要： With respect to input/output requests; a microprogram controls collection of data according to the data format; data accessing divides the requests for every recording medium and performs asynchronous processing; an on-line process is carried out in view of the processing priority order of the requests; parallel accessing sets requests for each medium; buffer control assures a block buffer and a page address list before receiving requests; data accessing sets a list of CCHHR codes in response to a continuous characteristic of the stored state in the recording medium; and mode deciding judges the two data transfer modes, a page search mode and a data search mode, in response to the requests.

摘要翻译： 关于输入/输出请求; 微程序根据数据格式控制数据采集; 数据访问对每个记录介质划分请求并进行异步处理; 考虑到请求的处理优先级顺序进行在线处理; 并行访问为每个介质设置请求; 缓冲器控制在接收请求之前确保块缓冲区和页面地址列表; 数据访问响应于记录介质中的存储状态的连续特性来设置CCHHR码的列表; 并且模式判定响应于请求来判断两种数据传送模式，寻呼模式和数据搜索模式。

公开(公告)号：US5239644A

公开(公告)日：1993-08-24

申请号：US758231

申请日：1991-09-09

申请人： Takaaki Seki ,  Hiroyuki Kitajima ,  Tadashi Ohsone ,  Hirofumi Nakagawa

发明人： Takaaki Seki ,  Hiroyuki Kitajima ,  Tadashi Ohsone ,  Hirofumi Nakagawa

IPC分类号： G06F13/14

CPC分类号： G06F13/14

摘要： A controller with a buffer is provided between a main memory and an external storage. This controller supplies a given request for access to the external storage and issues a preload request for a retrieval extent of the next access request by the time when data associated with this first access request is completely transferred to the buffer memory or to the main memory. Moreover, the controller stores the preloaded data in the buffer and, for the next access request, it transfers the data stored in the buffer to the main memory. Therefore, even when the host side (CPU) is processing, the access to the external storage can be made simultaneously, thus the response time and the operating ratio of the computer system being improved.

摘要翻译： 在主存储器和外部存储器之间提供具有缓冲器的控制器。 该控制器提供对外部存储器的访问的给定请求，并且在与该第一访问请求相关联的数据被完全传送到缓冲存储器或主存储器的时间时向下一个访问请求的检索范围发出预加载请求。 此外，控制器将预加载的数据存储在缓冲器中，并且对于下一个访问请求，它将存储在缓冲器中的数据传送到主存储器。 因此，即使主机侧（CPU）正在进行处理，也可以同时进行对外部存储器的访问，从而提高计算机系统的响应时间和运行率。

公开(公告)号：US4926324A

公开(公告)日：1990-05-15

申请号：US293555

申请日：1989-01-05

申请人： Akira Yamamoto ,  Miho Motoyama ,  Hiroyuki Kitajima ,  Takashi Doi ,  Toshifumi Nishimura

发明人： Akira Yamamoto ,  Miho Motoyama ,  Hiroyuki Kitajima ,  Takashi Doi ,  Toshifumi Nishimura

IPC分类号： G06F3/06 ,  G06F13/12

CPC分类号： G06F3/0601 ,  G06F13/122 ,  G06F2003/0698

摘要： An I/O control system includes an I/O control unit, a plurality of I/O devices, the start process prior to a data transfer process of the I/O device being off-line processed from the I/O control unit, and a data transfer path for data transferring to the I/O device, the data transfer being performed for one I/O device at a time. The I/O control unit controls an I/O device in such a way that the start process of the I/O device completes at the time when another I/O device under data transfer completes its data transfer, thus improving the utilization of a data transfer path.

摘要翻译： I / O控制系统包括I / O控制单元，多个I / O设备，在从I / O控制单元离线处理I / O设备的数据传送处理之前的开始处理， 以及用于数据传送到I / O设备的数据传输路径，一次为一个I / O设备执行数据传输。 I / O控制单元控制I / O设备，使得I / O设备的开始处理在数据传输的另一个I / O设备完成其数据传输时完成，从而提高了I / 数据传输路径。

公开(公告)号：US4542458A

公开(公告)日：1985-09-17

申请号：US495594

申请日：1983-05-18

申请人： Hiroyuki Kitajima ,  Kazuhiko Ohmachi ,  Mitsuru Doki ,  Junichi Kazama ,  Hidekazu Kanao

发明人： Hiroyuki Kitajima ,  Kazuhiko Ohmachi ,  Mitsuru Doki ,  Junichi Kazama ,  Hidekazu Kanao

IPC分类号： G06F12/00 ,  G06F9/50 ,  G06F17/30 ,  G06F1/00

CPC分类号： G06F9/5016

摘要： A method of assinging software resources such as files and programs to memory devices is disclosed which uses first storage for storing therein the access frequency to a memory device for causing each type of service request to utilize each of software resources and second storage for storing therein the processing speed, allowable utilization and storage capacity of each of memory devices and in which the allocation of each of said software resources to the memory devices is determined on the basis of information stored in the first and second storages so that a total time taken to access the memory devices is minimized while being restricted by the allowable utilization and storage capacity of each memory device.

摘要翻译： 公开了一种将诸如文件和程序的软件资源分配给存储器件的方法，其使用第一存储器将存储频率存储到存储器设备中，以使每种类型的服务请求利用软件资源中的每一个，并且存储其中的第二存储器 基于存储在第一和第二存储器中的信息，确定每个存储器件的处理速度，允许利用率和存储容量，并且其中将每个所述软件资源分配给存储器件，以便进行访问的总时间 存储器件被最小化，同时受到每个存储器件的允许利用率和存储容量的限制。

公开(公告)号：US4495570A

公开(公告)日：1985-01-22

申请号：US337812

申请日：1982-01-07

申请人： Hiroyuki Kitajima ,  Kazuhiko Ohmachi

发明人： Hiroyuki Kitajima ,  Kazuhiko Ohmachi

IPC分类号： G06F9/50 ,  G06F15/16 ,  G06F3/04

CPC分类号： G06F9/505 ,  G06F2209/503

摘要： A distributed processing system having a plurality of processors and/or terminals at a plurality of locations is provided with a processing request allocator which includes a device for storing the waiting time at each processor or terminal for beginning the execution of a service request as well as a device for storing the delay in communication from each location of a processor or terminal to each other processor or terminal in the system. The processing request allocator has a device for calculating the sums of the waiting time and delay for each route through the system where a processing request from a first location is executed by a predetermined processor and the processing result is sent to a second location within the system, and a device is provided for determining the minimum value of these sums to identify the processor or terminal to which the service request is to be allocated. Since a processor or terminal is selected to perform the processing of the service request on the basis of not only the waiting time at each processor but also the communication delay, the performance of the overall system is enhanced and the response time to each service request is minimized.

摘要翻译： 在多个位置具有多个处理器和/或终端的分布式处理系统设置有处理请求分配器，该处理请求分配器包括用于在每个处理器或终端处存储用于开始执行服务请求的等待时间的设备，以及 用于存储从处理器或终端的每个位置到系统中每个其他处理器或终端的通信延迟的设备。 处理请求分配器具有用于计算通过系统的每个路由的等待时间和延迟之和的设备，其中来自第一位置的处理请求由预定处理器执行，并且处理结果被发送到系统内的第二位置 并且提供用于确定这些和的最小值以识别要分配服务请求的处理器或终端的设备。 由于不仅选择处理器或终端来执行服务请求的处理，而且不仅基于每个处理器的等待时间，还包括通信延迟，从而增强了整个系统的性能，并且对每个服务请求的响应时间是 最小化。

公开(公告)号：US20120331364A1

公开(公告)日：2012-12-27

申请号：US13488741

申请日：2012-06-05

申请人： Toshiharu Sakai ,  Ryoji Azumi ,  Kiyomasa Nishisaka ,  Daisuke Hirata ,  Hiroyuki Kitajima

发明人： Toshiharu Sakai ,  Ryoji Azumi ,  Kiyomasa Nishisaka ,  Daisuke Hirata ,  Hiroyuki Kitajima

IPC分类号： G06F11/07

CPC分类号： H04L1/0052 ,  H03M13/1515 ,  H03M13/6561

摘要： An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.

摘要翻译： 纠错处理电路包括：分割电路，将输入数据分割为预定数据长度的多个片段; 多个并行设置的运算电路，分别对由分割电路分割的多条数据进行纠错运算; 多路复用电路，对由多个运算电路进行了运算的多条数据进行复用; 以及输出由多路复用电路复用的数据的输出电路。

公开(公告)号：US20070245176A1

公开(公告)日：2007-10-18

申请号：US11502517

申请日：2006-08-11

申请人： Shinji Sawane ,  Yuji Obana ,  Hiroyuki Kitajima

发明人： Shinji Sawane ,  Yuji Obana ,  Hiroyuki Kitajima

IPC分类号： G06F11/00

CPC分类号： H04L1/0061 ,  H04L1/203

摘要： In a BER monitoring circuit, error cycles of input data are detected by a parity check portion and an error cycle detecting portion, a maximum (average/median) value is detected from among the error cycles by an error cycle memory and an error cycle maximum (average/median) value retrieving portion. The value is converted into a corresponding estimated error rate by a Te-BER conversion table and an alarm is generated by an SF/SD detecting -portion when the estimated error rate exceeds an alarm detecting threshold. Thereafter, the alarm is released when the estimated error rate assumes equal to or less than an alarm releasing threshold. Also, an error-free detecting portion is activated when an alarm is generated and releases the alarm when a time period for which the error cycles stay flat exceeds a cycle corresponding to the alarm releasing threshold.

摘要翻译： 在BER监视电路中，通过奇偶校验部分和错误周期检测部分检测输入数据的错误周期，通过错误周期存储器和错误周期最大值检测错误周期中的最大值（平均值/中值） （平均/中值）检索部分。 当估计的误码率超过警报检测阈值时，该值被转换表转换成相应的估计错误率，并通过SF / SD检测产生警报。 此后，当估计误差率等于或小于报警释放阈值时，报警被释放。 此外，当产生报警时，无错误检测部分被激活，并且当错误周期保持平坦的时间段超过与报警释放阈值相对应的周期时，释放报警。