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公开(公告)号：US20190130858A1
公开(公告)日：2019-05-02
申请号：US15969129
申请日：2018-05-02
Inventor： Juncheng XIAO , Ronglei DAI
IPC: G09G3/36 , H03K17/687
Abstract: A gate driving circuit provided in the disclosure comprises a pull-up control module configured to generate a first control signal when power is turned off, a pull-up output module configured to output a high potential under control of the first control signal, a pull-down control module configured to generate a second control signal when power is turned off, and a pull-down output module configured to output a low potential under control of the second control signal. Wherein, the output terminals of the pull-up output module and the pull-down output module are connected to the output terminal of a Nth-stage gate driving unit, and, when power is turned off, the pull-up output module and the pull-down output module together make the output terminal of the Nth-stage gate driving unit output the high potential. The image remained on the liquid crystal screen when power is turned off suddenly is cleaned quickly thereby.
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公开(公告)号：US20190130851A1
公开(公告)日：2019-05-02
申请号：US15996808
申请日：2018-06-04
Inventor： Xiaojuan CUI , Xiang YANG
Abstract: The embodiments of the disclosure disclose an image processing method and an device thereof, by detecting the saturated color ratio of the current frame picture of the acquired target image to acquire a corresponding PWM duty ratio and gain coefficient, the method can intelligently control the backlight brightness of the display picture and the gain coefficient during the format conversion to solve the problem that the unsaturated color is darker than the saturated color when the picture is displayed, and the display effect of the terminal is improved.
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公开(公告)号：US20190129547A1
公开(公告)日：2019-05-02
申请号：US15970589
申请日：2018-05-03
Inventor： Ronglei DAI
IPC: G06F3/041 , G02F1/1345 , G09G3/36
CPC classification number: G06F3/0412 , G02F1/13454 , G06F3/0416 , G09G3/3677 , G09G2300/0408 , G09G2354/00
Abstract: The present application provides a single-type GOA circuit comprising a controllable signal setting unit for providing a controllable signal. The controllable signal is held at a potential of a constant low-level voltage source when the circuit is operated in normal status, and at a potential of a constant high-level voltage source when the circuit is in a transmission suspended period. The potential of the signals in the current leakage path in the transmission suspended period is changed in the application so that voltage controlling and leakage path eliminating could be achieved and stability of the circuit is increased.
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公开(公告)号：US20190129262A1
公开(公告)日：2019-05-02
申请号：US15580612
申请日：2017-11-21
IPC: G02F1/1362 , G02F1/1335 , G02F1/1368
Abstract: A liquid crystal display panel and a liquid crystal display device having the liquid crystal display panel are provided. The liquid crystal display panel includes a TFT array substrate and a color filter substrate disposed opposite to each other. The color filter substrate has a black matrix disposed thereon, the black matrix includes a first portion located in a display area and a second portion located in an non-display area. The second portion of the black matrix is provided with a groove surrounding the display area, the groove penetrates the black matrix in a thickness direction of the black matrix. The TFT array substrate is provided with a light shielding layer corresponding to a location where the groove is disposed, and a projection of the light shielding layer on the black matrix completely covers the groove.
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公开(公告)号：US10262618B2
公开(公告)日：2019-04-16
申请号：US15021461
申请日：2016-02-26
IPC: G09G3/36 , G02F1/13 , H03K17/687
Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
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Patent Agency Ranking
446.发明授权公开(公告)号：US10261372B2
公开(公告)日：2019-04-16
申请号：US15328130
申请日：2016-11-23
Inventor： Chunqian Zhang , Caiqin Chen
IPC: G02F1/1333 , G02F1/1343 , G02F1/1362 , H01L27/12 , H01L21/768 , H01L21/027 , H01L21/311
Abstract: The present application provides a manufacture method of an array substrate, wherein the manufacture method comprises providing a substrate; sequentially forming a planarization layer, a first common electrode layer and a first insulation layer on the substrate; forming a metal line layer on the first insulation layer; depositing a second insulation layer on a second metal layer and the first insulation layer; forming a plurality of through holes in the second insulation layer; forming a second common electrode layer on the second insulation layer which is formed with the through holes. The present application further provides a liquid crystal panel and a liquid crystal display screen.
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公开(公告)号：US10249246B2
公开(公告)日：2019-04-02
申请号：US15506236
申请日：2016-12-30
Inventor： Yafeng Li
IPC: G09G3/3266 , G09G3/3258 , G09G3/36
Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a tenth TFT (T10), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T9 and T10 so as to achieve forward and backward scanning without D2U and U2D control signals, which facilitates narrow border design and simplifies corresponding driving timing and reduce IC cost.
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公开(公告)号：US10247986B2
公开(公告)日：2019-04-02
申请号：US15327464
申请日：2016-12-27
Inventor： Jie Zeng , Xiaoling Li
IPC: G02F1/1335 , G02F1/1333 , F21V8/00
Abstract: Disclosed is a backlight module. The backlight module includes a backplane. The backplane is provided with a groove therethrough. Two sides and/or two ends of an optical diaphragm of the backlight module each are connected with a bendable flap which passes through the groove and is attached to the backplane. The backlight module has a simple structure without a plastic frame or a frame sealant, and an optical diaphragm in the backlight module can be fixed. A super narrow frame of the backlight module can be realized.
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公开(公告)号：US20190096346A1
公开(公告)日：2019-03-28
申请号：US15737308
申请日：2017-10-20
Inventor： Tingting ZHANG , Cong WANG
IPC: G09G3/36 , H01L27/12 , G02F1/1368 , G02F1/1362
CPC classification number: G09G3/3648 , G02F1/136286 , G02F1/1368 , G09G3/3677 , G09G2300/0819 , G09G2320/0233 , H01L27/124 , H01L27/1255
Abstract: The present disclosure relates to an array substrate and a display panel. The array substrate includes a plurality of scanning lines and a plurality of data lines intersecting with each other to form a plurality of pixel cells. The pixel cells are divided into the pixel cells within a first area and the pixel cells within a second area along the scanning lines. Each of the pixel cells within the second area includes a first thin film transistor (TFT) and a control unit connected to the first TFT. The control unit is configured to reduce a pixel voltage of the pixel cell where the first TFT is configured. As such, the display panel may display images uniformly, and display performance of the display panel may be improved.
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公开(公告)号：US20190096344A1
公开(公告)日：2019-03-28
申请号：US15516898
申请日：2017-03-15
Inventor： Qingcheng Zuo , Man Li , Xiaoling Yuan
IPC: G09G3/36
Abstract: The present invention provides a display driving circuit and a liquid crystal display panel with adding a first AND gate (AND1), a second AND gate (AND2) and a third AND gate (AND3). Two input ends of each of the three gates receives a branch control signal and a conditioning signal (BURR), and the conditioning signal (BURR) first performs several high and low voltage level conversions and then maintains the high voltage level, respectively in the high voltage level durations of the respective branch control signals to make the signal outputted by the output end of the first AND gate, the signal outputted by the output end of the second AND gate and the signal outputted by the output end of the third AND gate first perform several high and low voltage level conversions and then maintain the high voltage level.
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