Thermometer-code-to-binary encoders
    31.
    发明授权
    Thermometer-code-to-binary encoders 失效
    温度计代码到二进制编码器

    公开(公告)号:US07675440B1

    公开(公告)日:2010-03-09

    申请号:US12111146

    申请日:2008-04-28

    IPC分类号: H03M1/06

    CPC分类号: H03M1/0809 H03M7/165

    摘要: An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.

    摘要翻译: 提供了一种用于将温度计代码数据与气泡转换为二进制格式的编码器。 集成电路可以具有诸如数字锁相环电路的电路。 温度计代码数据字可以用作电路的控制信号。 可能希望通过集成电路上的控制逻辑来监测温度计代码数据字进行测试或下游处理。 编码器将温度计代码执行二进制编码,而不需要对温度计代码进行纠错以消除气泡。 可以使用气泡检测电路来检测温度计代码数据何时包含气泡。 编码器可以使用前置加法器和流水线级。

    Gray code to sign and magnitude converter
    32.
    发明授权
    Gray code to sign and magnitude converter 有权
    格雷码为符号和幅度转换器

    公开(公告)号:US07642938B2

    公开(公告)日:2010-01-05

    申请号:US12028469

    申请日:2008-02-08

    IPC分类号: H03M7/04

    CPC分类号: H03M7/16 H03M7/165

    摘要: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

    摘要翻译: 本发明涉及格雷码及其转换为符号和幅度表示。 格雷码用于闪存ADC(模数转换器),将模拟波形转换为采样二进制值。 这可以通过温度计代码来实现,并且本发明解决了由于不确定的温度计代码值导致的误差传播的问题。 特别地,本发明提供了一种格雷码,用于符号和幅度转换器,其被布置为产生除了符号位之外的其输出的比特,对于格雷码的相同代码,其与来自符号位改变值的边界相同的距离 格雷码按照它们的价值排列。

    DWA structure and method thereof, digital-to-analog signal conversion method and signal routing method
    33.
    发明授权
    DWA structure and method thereof, digital-to-analog signal conversion method and signal routing method 失效
    DWA结构及其方法,数模转换方式和信号路由方式

    公开(公告)号:US07486210B1

    公开(公告)日:2009-02-03

    申请号:US11835094

    申请日:2007-08-07

    IPC分类号: H03M7/00

    摘要: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.

    摘要翻译: 提供了包括第一延迟单元,二进制到温度计代码转换器,加法器,第二延迟单元,解码器,桶形移位器和多个信号线的数据加权平均(DWA)结构。 第一延迟单元延迟输入数字信号。 二进制到温度计代码转换器将第一延迟单元的输出信号转换成热代码。 第二延迟单元延迟加法器的输出信号。 加法器将输入数字信号加到第二延迟单元的输出信号上。 解码器解码第二延迟单元的输出信号。 桶形移位器根据解码器的输出信号从热代码生成输出信号。 信号线将桶形移位器的输出信号路由到两个独立的控制信号组。

    Fractional-Bit Systems
    34.
    发明授权
    Fractional-Bit Systems 失效
    分数位系统

    公开(公告)号:US07071849B2

    公开(公告)日:2006-07-04

    申请号:US10907381

    申请日:2005-03-31

    申请人: Guobiao Zhang

    发明人: Guobiao Zhang

    IPC分类号: H03M5/02

    摘要: The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized.

    摘要翻译: 本发明放弃了将每个单元比特位b递增1的常规方法,但是允许每个单元格N之间的状态逐次增加,产品世代之间只有1个。 由于N不再是2的整数幂,所以b取小数值,产生一个分数位系统。 在小数位系统中,以单位为单位对单元进行解码。 通过调整字宽,可以优化系统效率。

    Apparatus and method for assigning circuit card base addresses using thermometer codes
    35.
    发明申请
    Apparatus and method for assigning circuit card base addresses using thermometer codes 审中-公开
    使用温度计代码分配电路卡基地址的装置和方法

    公开(公告)号:US20060061493A1

    公开(公告)日:2006-03-23

    申请号:US10946788

    申请日:2004-09-22

    IPC分类号: H03M7/00

    CPC分类号: H03M7/165

    摘要: In plurality of series-coupled circuit boards, a thermometer code is used to provide the address signals for the circuit board. Each terminal of the circuit board input connector is coupled next successive terminal of the circuit board output connector. The terminals of the circuit board input connectors are coupled, through a pull-up resistor, to a voltage source. The least significant terminal of the output terminal can provide a logic signal opposite to the logic signal provided by the voltage source. The address lines for the circuit board are coupled to the terminals of the input connector. In this manner a thermometer address code can be provided for the sequence of series-coupled circuit boards. According to the present invention, the thermometer codes can be expanded with selected additional apparatus.

    摘要翻译: 在多个串联电路板中,使用温度计代码为电路板提供地址信号。 电路板输入连接器的每个端子连接在电路板输出连接器的下一个连续的端子上。 电路板输入连接器的端子通过上拉电阻耦合到电压源。 输出端子的最低有效端子可以提供与由电压源提供的逻辑信号相反的逻辑信号。 电路板的地址线耦合到输入连接器的端子。 以这种方式,可以为串联电路板的顺序提供温度计地址代码。 根据本发明,可以使用所选择的附加装置来扩展温度计代码。

    Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter
    36.
    发明授权
    Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter 有权
    模数转换器以及用于产生用于模数转换器的中间码的方法

    公开(公告)号:US07002502B2

    公开(公告)日:2006-02-21

    申请号:US10498765

    申请日:2002-12-12

    IPC分类号: H03M1/36

    CPC分类号: H03M7/165

    摘要: Analog-to-digital converter for converting an analog input signal into a digital binary output signal includes a reference unit for generating a thermometric signal based on comparison of the input signal with a reference voltage level, a first logic circuit connected to the reference unit for generating an intermediate signal based on the thermometric signal, and a second logic circuit connected to the first logic circuit for generating the digital binary output signal based on the intermediate signal. The thermometric signal includes a bit word from a first set of bit words and the intermediate signal includes a bit word from a second set of bit words. Bit words from the second set are arranged in rows of a matrix, the sequence of the rows corresponding to unique numbers represented by the bit words. Respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.

    摘要翻译: 用于将模拟输入信号转换为数字二进制输出信号的模数转换器包括用于基于输入信号与参考电压电平的比较产生测温信号的参考单元,连接到参考单元的第一逻辑电路,用于 基于所述测温信号生成中间信号;以及第二逻辑电路,连接到所述第一逻辑电路,用于基于所述中间信号产生所述数字二进制输出信号。 测温信号包括来自第一组位字的位字,并且中间信号包括来自第二组位字的位字。 来自第二组的位字被排列成矩阵的行,行的顺序与由位字表示的唯一数相对应。 矩阵的相应列中的相应数量的位变化至少基本相等。

    Fractional-Bit Systems
    37.
    发明申请
    Fractional-Bit Systems 失效
    分数位系统

    公开(公告)号:US20050219077A1

    公开(公告)日:2005-10-06

    申请号:US10907381

    申请日:2005-03-31

    申请人: Guobiao Zhang

    发明人: Guobiao Zhang

    IPC分类号: H03M7/16 H03M7/34

    摘要: The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized.

    摘要翻译: 本发明放弃了将每个单元比特位b递增1的常规方法,但是允许每个单元格N之间的状态逐次增加,产品世代之间只有1个。 由于N不再是2的整数幂,所以b取小数值,产生一个分数位系统。 在小数位系统中,以单位为单位对单元进行解码。 通过调整字宽,可以优化系统效率。

    Encoder circuit and A/D conversion circuit
    38.
    发明申请
    Encoder circuit and A/D conversion circuit 失效
    编码器电路和A / D转换电路

    公开(公告)号:US20050134495A1

    公开(公告)日:2005-06-23

    申请号:US11057753

    申请日:2005-02-15

    摘要: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.

    摘要翻译: 希望提供一种编码器电路和A / D转换器,其可以将关于温度计代码的所有可能组合的编码器输出的误差最小化。 为此,编码器电路的逻辑被配置为将温度计代码作为输入,并且将编码值作为编码值输出一个或多个编码值被分配的范围的中心值,所述一个或多个编码值对应于 到温度计代码中出现的“0”和“1”之间的一个或多个边界的位置。

    Neural networks and neural memory
    39.
    发明申请
    Neural networks and neural memory 审中-公开
    神经网络和神经记忆

    公开(公告)号:US20050049984A1

    公开(公告)日:2005-03-03

    申请号:US10960032

    申请日:2004-10-08

    申请人: Douglas King

    发明人: Douglas King

    摘要: A neural pattern matcher is made up of an array of first sum and threshold SAT1 devices 18 each of which receives a number of inputs and a threshold value, and fires a 1 output if the number of inputs exceeds the threshold value. The outputs of the array of the SAT1 devices may be considered as a 2D image or generic template against which new data supplied into the registers 26 making up a data plane 24 are correlated at a correlation plane 20 of EX-NOR gates 22. The outputs of the EX-NOR gates themselves may be summed and thresholded by a seconded sum and threshold device 28 to provide a neural output ‘1’ or ‘0’ indicating match or no match. The matcher may therefore behave as a neural auto-associative memory which continually adapts to the input data to recognize data of a particular specified class.

    摘要翻译: 神经模式匹配器由第一和阈值SAT1装置18的阵列组成,每个SAT1装置接收多个输入和阈值,并且如果输入数量超过阈值则触发1个输出。 SAT1装置的阵列的输出可以被认为是2D图像或通用模板,其中提供给构成数据平面24的寄存器26中的新数据在EX-NOR门22的相关平面20处被相关。输出 可以由二次和和阈值装置28对EX-NOR门本身进行求和和阈值,以提供指示匹配或不匹配的神经输出“1”或“0”。 因此,匹配器可以作为神经自动关联存储器,其连续地适应输入数据以识别特定指定类的数据。

    Pulse width modulation systems and methods
    40.
    发明授权
    Pulse width modulation systems and methods 有权
    脉宽调制系统及方法

    公开(公告)号:US06822588B1

    公开(公告)日:2004-11-23

    申请号:US10825577

    申请日:2004-04-15

    IPC分类号: H03M700

    CPC分类号: H03M7/165

    摘要: Pulse width modulation systems and methods are described. In one aspect, a pulse width modulation system includes a register and a code word generator. The code word generator has an input for receiving a specified output frequency and a specified duty cycle and is operable to generate code words of different lengths. The code word generator is operable to generate a base code word having a length set to achieve the specified output frequency and having a thermometer code value set in accordance with the specified duty cycle. The code word generator is further operable to load the register with a code word pattern including a sequence of one or more copies of the base code word.

    摘要翻译: 描述了脉宽调制系统和方法。 一方面,脉宽调制系统包括寄存器和码字发生器。 码字生成器具有用于接收指定的输出频率和指定的占空比的输入,并且可操作以产生不同长度的码字。 码字生成器可操作以产生具有设定长度的基本码字,以实现指定的输出频率并具有根据指定的占空比设置的温度计代码值。 代码字产生器还可操作以用包括基本代码字的一个或多个副本的序列的代码字模式加载寄存器。