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    STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
    31.
    发明申请
    STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE 有权
    半导体器件结构的结构与形成方法

    公开(公告)号：US20170062561A1

    公开(公告)日：2017-03-02

    申请号：US14840904

    申请日：2015-08-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-Yi PENG ,  Chih-Chieh YEH ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

    IPC: H01L29/06 ,  H01L21/322

    CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.

    Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的鳍结构。 翅片结构包括第一表面和第二表面。 第一表面倾斜于第二表面。 半导体器件结构还包括覆盖翅片结构的第一表面和第二表面的钝化层。 覆盖第一表面的钝化层的第一部分的厚度与覆盖第二表面的钝化层的第二部分的厚度基本相同。

    DEVICE HAVING EXTENDED SOURCE/DRAIN CONTACT AND METHOD
    32.
    发明申请
    DEVICE HAVING EXTENDED SOURCE/DRAIN CONTACT AND METHOD 有权

    公开(公告)号：US20250040183A1

    公开(公告)日：2025-01-30

    申请号：US18361051

    申请日：2023-07-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Hao CHANG ,  Wei-Yang LEE ,  Kuan-Hao CHENG ,  Cheng-Yi PENG

    IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.

    FINFET FABRICATION METHODS
    33.
    发明申请
    FINFET FABRICATION METHODS 有权

    公开(公告)号：US20240371970A1

    公开(公告)日：2024-11-07

    申请号：US18772213

    申请日：2024-07-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun Hsiung TSAI ,  Cheng-Yi PENG ,  Yin-Pin WANG ,  Kuo-Feng YU ,  Da-Wen LIN ,  Jian-Hao CHEN ,  Shahaji B. MORE

    IPC: H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234

    Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

    Spacer Structures for Semiconductor Devices
    34.
    发明申请
    Spacer Structures for Semiconductor Devices 有权

    公开(公告)号：US20210280716A1

    公开(公告)日：2021-09-09

    申请号：US16807303

    申请日：2020-03-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Yi PENG ,  Song-Bor LEE

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

    Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

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