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公开(公告)号：US10447958B2
公开(公告)日：2019-10-15
申请号：US16149023
申请日：2018-10-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yibing Michelle Wang , Ilia Ovsiannikov
Abstract: Using the same image sensor to capture a two-dimensional (2D) image and three-dimensional (3D) depth measurements for a 3D object. A laser point-scans the surface of the object with light spots, which are detected by a pixel array in the image sensor to generate the 3D depth profile of the object using triangulation. Each row of pixels in the pixel array forms an epipolar line of the corresponding laser scan line. Timestamping provides a correspondence between the pixel location of a captured light spot and the respective scan angle of the laser to remove any ambiguity in triangulation. An Analog-to-Digital Converter (ADC) in the image sensor operates as a Time-to-Digital (TDC) converter to generate timestamps. A timestamp calibration circuit is provided on-board to record the propagation delay of each column of pixels in the pixel array and to provide necessary corrections to the timestamp values generated during 3D depth measurements.
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公开(公告)号：US09703208B2
公开(公告)日：2017-07-11
申请号：US14714245
申请日：2015-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yibing Michelle Wang , Duhyun Lee
CPC classification number: G03F7/70291 , G02F1/0121 , G02F1/017
Abstract: MQW devices, IC chips and methods may be used in semiconductor lithography patterning systems. An MQW device includes an array of pixels that have transmission elements and associated support circuits. The support circuits have preliminary memory cells and final memory cells. The final memory cells store transmittance values that control transmittances of the associated transmission elements. This way, exposure of a target with a lithography system for purposes of patterning the target may be performed through the transmission elements according to the controlled transmittances, while subsequent transmittance values are being received by the preliminary memory cells from memory banks. The exposure of the target therefore needs to pause for less time, in order to wait for the MQW device to be refreshed with the subsequent transmittance values. Accordingly the whole semiconductor lithography patterning system may operate faster and thus have more throughput.
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33.发明授权Unit pixel of stacked image sensor and stacked image sensor including the same 有权堆叠图像传感器的单位像素和包括其的堆叠图像传感器公开(公告)号：US09350930B2
公开(公告)日：2016-05-24
申请号：US14453124
申请日：2014-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-Yon Lee , Yibing Michelle Wang , Gwi-deok Ryan Lee
IPC: H01L27/00 , H04N5/378 , H01L27/146
CPC classification number: H04N5/378 , H01L27/14609 , H01L27/14627 , H01L27/14641 , H01L27/14643 , H01L27/14665 , H04N5/37457 , H04N9/045
Abstract: A unit pixel of a stacked image sensor includes a stacked photoelectric conversion unit, a first and second signal generating units. The stacked photoelectric conversion unit includes first, second and third photoelectric conversion elements that are stacked on each other. The first, second and third photoelectric conversion elements collect first, second and third photocharges based on first, second and third components of incident light. The first signal generating unit generates a first pixel signal based on the first photocharges and a first signal node and generates a second pixel signal based on the second photocharges and the first signal node. The second signal generating unit generates a third pixel signal based on the third photocharges and a second signal node. At least a portion of the second signal generating unit is shared by the first signal generating unit.
Abstract translation: 层叠图像传感器的单位像素包括层叠光电转换单元，第一和第二信号生成单元。 叠层光电转换单元包括彼此堆叠的第一，第二和第三光电转换元件。 第一，第二和第三光电转换元件基于入射光的第一，第二和第三分量收集第一，第二和第三光电荷。 第一信号产生单元基于第一光电荷产生第一像素信号和第一信号节点，并且基于第二光电荷和第一信号节点生成第二像素信号。 第二信号生成单元基于第三光电荷产生第三像素信号和第二信号节点。 第二信号生成单元的至少一部分由第一信号生成单元共享。
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公开(公告)号：US20250083149A1
公开(公告)日：2025-03-13
申请号：US18491602
申请日：2023-10-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shailabh Kumar , Vinayak Narasimhan , Hyuck Choo , Radwanul Hasan Siddique , Yibing Michelle Wang
IPC: B01L7/00
Abstract: A nucleic acid amplification system includes a single use chemical heater, a fluidic consumable on the single use chemical heater that is configured to contain a test sample including target nucleic acids, a multi-use heater configured to heat the single use chemical heater and/or the fluidic consumable, a temperature sensor configured to measure a temperature of the test sample in the fluidic consumable, a computer device including a processor, a non-volatile memory device, and a controller that is configured to control the multi-use heater, and a detection system configured to detect the target nucleic acids.
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公开(公告)号：US12192670B2
公开(公告)日：2025-01-07
申请号：US17950083
申请日：2022-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yibing Michelle Wang , Kwang Oh Kim , Radwanul Hasan Siddique
IPC: H04N5/33 , H01L27/146
Abstract: A pixel for an image sensor includes a microbolometer sensor portion, a visible image sensor portion and an output path. The microbolometer sensor portion outputs a signal corresponding to an infrared (IR) image sensed by the microbolometer sensor portion. The visible image sensor portion outputs a signal corresponding to a visible image sensed by the visible image sensor portion. The output path is shared by the microbolometer and the visible image sensor portions, and is controlled to selectively output the signal corresponding to the IR image or the signal corresponding to the visible image. The output path may be further shared with a visible image sensor portion of an additional pixel, in which case the output path may be controlled to selectively to also output the signal corresponding to a visible image of the additional pixel.
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Patent Agency Ranking
公开(公告)号：US11924545B2
公开(公告)日：2024-03-05
申请号：US17941000
申请日：2022-09-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Yibing Michelle Wang , Gregory Waligorski , Qiang Zhang
IPC: H04N23/00 , G06T7/521 , H04N23/667
CPC classification number: H04N23/667 , G06T7/521 , H04N2213/003
Abstract: Two-dimensional (2D) color information and 3D-depth information are concurrently obtained from a 2D pixel array. The 2D pixel array is arranged in a first group of a plurality of rows. A second group of rows of the array are operable to generate 2D-color information and pixels of a third group of the array are operable to generate 3D-depth information. The first group of rows comprises a first number of rows, the second group of rows comprises a second number of rows that is equal to or less than the first number of rows, and the third group of rows comprises a third number of rows that is equal to or less than the second number of rows. In an alternating manner, 2D-color information is received from a row selected from the second group of rows and 3D-depth information is received from a row selected from the third group of rows.
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公开(公告)号：US11847790B2
公开(公告)日：2023-12-19
申请号：US17943068
申请日：2022-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yibing Michelle Wang , Kwang Oh Kim , Lilong Shi
IPC: G06T7/521
CPC classification number: G06T7/521 , G06T2207/10028 , G06T2207/10152
Abstract: A camera system. In some embodiments, the camera system includes a first laser, a camera, and a processing circuit connected to the first laser and to the camera. The first laser may be steerable, and the camera may include a pixel including a photodetector and a pixel circuit, the pixel circuit including a first time-measuring circuit.
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公开(公告)号：US11783161B2
公开(公告)日：2023-10-10
申请号：US16446610
申请日：2019-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
CPC classification number: G06N3/04 , G06F17/153 , G06F17/16 , G06N3/08 , G06T9/002 , G06F9/3001
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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公开(公告)号：US11775802B2
公开(公告)日：2023-10-03
申请号：US16552945
申请日：2019-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
CPC classification number: G06N3/04 , G06F17/153 , G06F17/16 , G06N3/08 , G06T9/002 , G06F9/3001
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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公开(公告)号：US11775801B2
公开(公告)日：2023-10-03
申请号：US16552850
申请日：2019-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
CPC classification number: G06N3/04 , G06F17/153 , G06F17/16 , G06N3/08 , G06T9/002 , G06F9/3001
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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