Abstract:
A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.
Abstract:
A display device includes: a display unit including a plurality of pixels, each of the pixels including: an OLED; and a driving transistor to supply current to an anode of the OLED according to a voltage applied to a gate of the driving transistor and a power supply voltage; a scan driver to supply scan signals to the pixels; an initialization driver to supply initializing signals to the pixels; a data driver to supply data signals to the pixels; light emission drivers to supply first and second light emission signals to the pixels; and a power supply to supply the power supply voltage and an initialization voltage to the pixels, wherein the initialization voltage is supplied to the anode during a first period, and the power supply voltage corresponding to a threshold voltage of the driving transistor is supplied to the gate during a first sub-period of the first period.
Abstract:
A display device of the invention includes: a pixel portion including first pixel rows connected to first scan lines and second pixel rows connected to second scan lines; a scan driver including first and second stages connected to the first scan lines and the second scan lines; and a data driver connected to the first and second pixel rows through same data lines. The first stages are connected to first clock lines, the second stages are connected to second clock lines, a first start stage of the first stages and a second start stage of the second stages are connected to a same scan start line, each first stage excluding the first start stage is connected to a first scan line of a previous first stage, and each second stage excluding the second start stage is connected to a second scan line of a previous second stage.
Abstract:
The present disclosure provides a display device that controls output of a scan signal, conversion of image data, and output of a data signal in response to partial scan driving. The display device includes a display panel driven in one of a first mode and a second mode, a scan driver sequentially supplying a scan signal for writing data in the first mode, a controller generating image data in which input image data is rearranged based on the first mode or the second mode, and a data driver converting the image data into data signals and supplying the data signals to output channels.
Abstract:
A display device includes: a display panel configured to display an image; a signal controller configured to determine whether an input image signal is a still image signal, and determine color coordinates using data values of one frame data of the input image signal, and generate compensated image data by compensating image data of the one frame data based on the color coordinates; and a data driver configured to generate a data signal based on the compensated image data and output the compensated image data to the display panel through a data line.
Abstract:
A display system and a driving method for a display system that includes an application processor configured to supply a mode control signal corresponding to a plurality of driving modes and input image data corresponding thereto; and a display module that includes pixels configured to display an image and configured to control any one of a plurality of gamma values and power source voltages supplied to the pixels in response to the plurality of driving modes.
Abstract:
A display device according to an embodiment of the disclosure includes a timing controller, a scan driver including a plurality of stages connected to a plurality of clock signal lines and generating a plurality of scan signals in response to the scan start signal, a data driver configured to generate a plurality of data signals based on the image data, and a pixel portion including a plurality of pixels. One stage in the scan driver transmits a carry signal to 2n-th next stage. The timing controller selects any one of a normal frequency and low frequencies lower than the normal frequency as a driving frequency based on the input image data, and adjusts a clock duty of the plurality of clock signals so that a time required to output all of the plurality of scan signals during one frame is constant irrespective of the driving frequency.
Abstract:
A display device includes a display panel including a plurality of pixels, a data driver which provides data signals to the plurality of pixels, and a controller which controls the data driver. The controller writes frame data to a frame memory, reads the frame data in each of a plurality of frame periods, performs in a first frame period of the plurality of frame periods a still image detection operation that determines whether the frame data represent a still image, and does not performs the still image detection operation in a second frame period of the plurality of frame periods subsequent to the first frame period.
Abstract:
A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.
Abstract:
A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.