公开(公告)号：US09342166B2

公开(公告)日：2016-05-17

申请号：US13658726

申请日：2012-10-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Joon Cho ,  Joon-Chul Goh ,  Ji-Hong Park ,  Cheol-Gon Lee ,  Chong-Chul Chai ,  Jae-Keun Lim

IPC: G06F3/041 ,  G06F3/044

CPC classification number: G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04111

Abstract: In a touch substrate and a display apparatus, the touch substrate includes a first electrode, a second electrode, a first touch electrode and a blocking layer. The first electrode includes an opaque conductive material and extends along a first direction. The second electrode includes the opaque conductive material, extends along a second direction crossing the first direction, and has a gap through which the first electrode extends. The first touch electrode is formed on the first electrode and is electrically connected to the first electrode. The blocking layer overlaps the first and second electrodes.

Abstract translation: 在触摸基板和显示装置中，触摸基板包括第一电极，第二电极，第一触摸电极和阻挡层。 第一电极包括不透明导电材料并且沿着第一方向延伸。 第二电极包括不透明导电材料，沿着与第一方向交叉的第二方向延伸，并且具有第一电极延伸穿过的间隙。 第一触摸电极形成在第一电极上并与第一电极电连接。 阻挡层与第一电极和第二电极重叠。

公开(公告)号：US12087228B2

公开(公告)日：2024-09-10

申请号：US18123334

申请日：2023-03-20

Applicant: Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang University

Inventor： Chong-Chul Chai ,  Oh-Kyong Kwon ,  Nack-Hyeon Keum ,  Kyong-Hwan Oh ,  Young-Wan Seo ,  Yong-Koo Her ,  In-Jae Hwang

IPC: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0866 ,  G09G2310/063 ,  G09G2320/02 ,  G09G2320/043 ,  G09G2330/021

Abstract: A display apparatus includes a plurality of pixels. A pixel includes a first capacitor connected between a first voltage line receiving a first driving signal and a first node, a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal and a second electrode connected to a second node, an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal, a second capacitor connected between an m-th data line and the second node (wherein, ‘m’ is a natural number) and a second transistor comprising a control electrode connected to an n-th scan line (wherein, ‘n’ is a natural number), a first electrode connected to the first node and a second electrode connected to the second node.

公开(公告)号：US10283054B2

公开(公告)日：2019-05-07

申请号：US15696734

申请日：2017-09-06

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun-Hyun Park ,  An-Su Lee ,  Ji-Hye Lee ,  Bo-Yong Chung ,  Kang-Moon Jo ,  Chong-Chul Chai

IPC: G09G3/3266 ,  G09G3/3258 ,  G09G3/3291

Abstract: A pixel includes first to fourth transistors and a driving transistor. The first transistor is connected between a data line and a first node and has a gate electrode to receive a scan signal. The driving transistor is connected between the first node and a second node and has a gate electrode connected to a third node. The second transistor is connected between the second and third nodes and has a gate electrode to receive the scan signal. The third transistor is connected between first power and the first node and has a gate electrode to receive an emission signal. The fourth transistor is connected between the first and second nodes and has a gate electrode to receive an initialization signal. An organic light emitting diode is connected between the second node and second power. A storage capacitor is connected between the first power and third node.

公开(公告)号：US10134352B2

公开(公告)日：2018-11-20

申请号：US15383686

申请日：2016-12-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

IPC: G09G3/36

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

公开(公告)号：US09576547B2

公开(公告)日：2017-02-21

申请号：US14538589

申请日：2014-11-11

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang-Chul Jung ,  Chong-Chul Chai ,  Mee-Hye Jung

IPC: G09G5/02 ,  G09G3/36 ,  G02F1/1362 ,  G02F1/1343

CPC classification number: G09G3/3696 ,  G02F1/134363 ,  G02F1/13624 ,  G02F2001/134345 ,  G02F2201/124 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2300/0434 ,  G09G2300/0814 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2320/0219

Abstract: A display panel includes a first sub-pixel electrode and a second sub-pixel electrode alternating with each other to form a horizontal electric field, a first data line transmitting a first data voltage to the first sub-pixel electrode, and a second data line transmitting a second data voltage to the second sub-pixel electrode, wherein the second sub-pixel electrode is formed to overlap the first and second data lines.

Abstract translation: 显示面板包括彼此交替以形成水平电场的第一子像素电极和第二子像素电极，向第一子像素电极发送第一数据电压的第一数据线和第二数据线 向第二子像素电极发送第二数据电压，其中第二子像素电极形成为与第一和第二数据线重叠。

公开(公告)号：US09401122B2

公开(公告)日：2016-07-26

申请号：US14322983

申请日：2014-07-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Eun Jo ,  Kyoung-Ju Shin ,  Chong-Chul Chai

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G5/00 ,  G09G3/3677 ,  G09G2300/0408

Abstract: A display panel includes a display area including a gate line and a data line, a gate driver integrated on a substrate and connected to one end of the gate line, the gate driver including a plurality of a stage, a signal line connected to the stages; and a blocking member disposed on the signal line and overlapped with the signal line, the blocking member including a plurality of an opening.

Abstract translation: 显示面板包括：显示区域，包括栅极线和数据线;集成在基板上并连接到栅极线的一端的栅极驱动器，栅极驱动器包括多个级，连接到级的信号线 ; 以及阻挡构件，其设置在所述信号线上并与所述信号线重叠，所述阻挡构件包括多个开口。

公开(公告)号：US20160140914A1

公开(公告)日：2016-05-19

申请号：US15003189

申请日：2016-01-21

Applicant: Samsung Display Co., Ltd.

Inventor： Kyoung-Ju Shin ,  Chong-Chul Chai ,  Eun-Ju Kim

IPC: G09G3/34 ,  G02B26/04 ,  G09G3/20

CPC classification number: G09G3/3433 ,  G02B26/02 ,  G02B26/04 ,  G09G3/2007 ,  G09G3/2081 ,  G09G3/3466 ,  G09G5/10 ,  G09G2300/04 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/08

Abstract: A display apparatus includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel of the plurality of pixels comprises a switching device coupled to a corresponding gate line of the plurality of gate lines and to a corresponding data line of the plurality of data lines, a micro-electro-mechanical system coupled to an output electrode of the switching device, and a control device coupled to the output electrode of the switching device. The control device comprises a storage capacitor coupled to the output electrode of the switching device and a coupling capacitor coupled to the output electrode of the switching device, the storage capacitor connected in parallel with the coupling capacitor. The output electrode of the switching device, the storage capacitor, the coupling capacitor, and a first electrode of the micro-electro-mechanical system are all directly connected to each other.

Abstract translation: 显示装置包括多条栅极线，多条数据线和多个像素。 多个像素的每个像素包括耦合到多个栅极线中的相应栅极线和多个数据线的对应数据线的开关器件，耦合到该多个栅极线的输出电极的微电子机械系统 开关装置，以及耦合到开关装置的输出电极的控制装置。 控制装置包括耦合到开关装置的输出电极的存储电容器和耦合到开关装置的输出电极的耦合电容器，该存储电容器与耦合电容器并联连接。 开关器件的输出电极，存储电容器，耦合电容器以及微电子机械系统的第一电极都直接连接在一起。

公开(公告)号：US20160104424A1

公开(公告)日：2016-04-14

申请号：US14663143

申请日：2015-03-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Chong-Chul Chai ,  Joon-Chul Goh ,  Mu-Kyung Jeon

IPC: G09G3/32 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G2300/0852 ,  G09G2310/0262 ,  G09G2310/0278 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78648

Abstract: A pixel, a display device having the same, and a thin film transistor (TFT) substrate for the display device are disclosed. In one aspect, the pixel includes an emitter configured to emit light based at least in part on a driving current. The pixel also includes a driving transistor including an active layer, a first electrode electrically connected to a first end portion of the active layer, a second electrode electrically connected to a second end portion of the active layer, a first gate electrode configured to receive a data voltage from a data driver so as to form a channel in the active layer, and a second gate electrode configured to receive a bias voltage from a voltage source, wherein the channel is configured to adjust the driving current.

Abstract translation: 公开了一种像素，具有该像素的显示装置和用于显示装置的薄膜晶体管（TFT）基板。 在一个方面，像素包括被配置为至少部分地基于驱动电流发光的发射器。 该像素还包括驱动晶体管，其包括有源层，与有源层的第一端部电连接的第一电极，与该有源层的第二端部电连接的第二电极，被配置为接收 来自数据驱动器的数据电压，以便在有源层中形成通道;以及第二栅电极，被配置为从电压源接收偏置电压，其中该通道被配置为调节驱动电流。

公开(公告)号：US09293093B2

公开(公告)日：2016-03-22

申请号：US14231001

申请日：2014-03-31

Applicant: Samsung Display Co., LTD.

Inventor： Jong-Hee Kim ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/08

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract translation: 栅极驱动器电路包括第N级（“N”是自然数）第N级（“N”是自然数）包括被配置为使用第n级输出第N门信号的上拉部分 响应于所述控制节点的节点信号的第一时钟信号，被配置为响应于所述控制节点的节点信号而使用所述第一时钟信号输出第N进位信号的进位部分，连接到所述控制节点的第一输出部分 并且被配置为响应于具有比第一时钟信号（'n'是自然数）短的周期的第二时钟信号，使用第N个门信号输出第n个门信号，第二 输出部分连接到第（n + 1）栅极线，并被配置为响应于具有与第二栅极相反相位的第二反相时钟信号，使用第N栅极信号输出第（n + 1）栅极信号 时钟信号。

公开(公告)号：US20150042638A1

公开(公告)日：2015-02-12

申请号：US14456976

申请日：2014-08-11

Applicant: SAMSUNG DISPLAY CO., LTD. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。