Semiconductor device having separate initialization voltage lines

    公开(公告)号:US11455943B2

    公开(公告)日:2022-09-27

    申请号:US17187996

    申请日:2021-03-01

    Abstract: A display device includes a substrate, a polycrystalline semiconductor layer including a channel of a driving transistor, and a channel of a seventh transistor, a gate electrode of the driving transistor overlapping the channel thereof, a gate electrode of the seventh transistor overlapping the channel thereof, an oxide semiconductor layer including a channel of a fourth transistor, a gate electrode thereof overlapping the channel of the fourth transistor, a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being position on a same layer, and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being positioned on different layers from each other.

    Display device
    32.
    发明授权

    公开(公告)号:US11302753B2

    公开(公告)日:2022-04-12

    申请号:US16843236

    申请日:2020-04-08

    Abstract: A display device includes: a substrate that includes a first area and a second area; a plurality of pixels included in the first area; and a dummy pattern included in the second area, wherein a size of the dummy pattern is smaller than a pixel area corresponding to a first pixel among the plurality of pixels, a ratio of an area occupied by a pixel pattern of the first pixel with respect to the pixel area is a first value, a ratio of an area occupied by the dummy pattern with respect to a dummy area is a second value that is greater than the first value, and the dummy area and the pixel area have the same size as each other.

    Display device
    33.
    发明授权

    公开(公告)号:US11302268B2

    公开(公告)日:2022-04-12

    申请号:US17193281

    申请日:2021-03-05

    Abstract: A display device includes a substrate, a first active pattern, a first gate electrode, a second active pattern, a second gate electrode, a first connecting pattern, and a second connecting pattern. The first connecting pattern is disposed on the second active pattern and is electrically connected to the first gate electrode, and the second connecting pattern is disposed on the first connecting pattern and is electrically connected to the first connecting pattern and the second active pattern.

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