公开(公告)号：US20240281397A1

公开(公告)日：2024-08-22

申请号：US18192631

申请日：2023-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Michele ROSSI ,  Giuseppe DESOLI ,  Thomas BOESCH

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F13/1668

Abstract: A hardware accelerator includes processing elements of a neural network, each processing element having a memory; a stream switch; stream engines coupled to functional circuits via the stream switch, wherein the stream engines, in operation, generate data streaming requests to stream data to and from functional circuits of the plurality of functional circuits; a first system bus interface coupled to the stream engines; a second system bus interface coupled to the processing elements; and mode control circuitry, which, in operation, sets respective modes of operation for the plurality of processing elements. The modes of operation include: a compute mode of operation in which the processing element performs computing operations using the memory associated with the processing element; and a memory mode of operation in which the memory associated with the processing element performs memory operations, bypassing the stream switch, via the second system bus interface.

公开(公告)号：US20230153621A1

公开(公告)日：2023-05-18

申请号：US18156704

申请日：2023-01-19

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal SINGH ,  Giuseppe DESOLI ,  Thomas BOESCH

IPC: G06N3/08 ,  G06N20/00 ,  G06F17/11 ,  G06N3/063 ,  G06F9/30 ,  G06N3/045

CPC classification number: G06N3/08 ,  G06N20/00 ,  G06F17/11 ,  G06N3/063 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06N3/045

Abstract: An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.

公开(公告)号：US20230084985A1

公开(公告)日：2023-03-16

申请号：US18056937

申请日：2022-11-18

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Thomas BOESCH ,  Giuseppe DESOLI ,  Surinder Pal SINGH ,  Carmine CAPPETTA

IPC: G06N3/063 ,  G06F9/50 ,  H03M7/30

Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.

公开(公告)号：US20230062910A1

公开(公告)日：2023-03-02

申请号：US17461626

申请日：2021-08-30

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Giuseppe DESOLI ,  Surinder Pal SINGH ,  Thomas BOESCH

IPC: G06N3/063 ,  G06N3/04 ,  G06F9/50

Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

公开(公告)号：US20220101086A1

公开(公告)日：2022-03-31

申请号：US17039653

申请日：2020-09-30

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Carmine CAPPETTA ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/04 ,  G06N3/063 ,  G06F9/38 ,  G06T7/11

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

公开(公告)号：US20210397933A1

公开(公告)日：2021-12-23

申请号：US16909673

申请日：2020-06-23

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Thomas BOESCH ,  Giuseppe DESOLI ,  Surinder Pal SINGH ,  Carmine CAPPETTA

IPC: G06N3/063 ,  G06F9/50 ,  H03M7/30

Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.

公开(公告)号：US20210256346A1

公开(公告)日：2021-08-19

申请号：US16794062

申请日：2020-02-18

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe DESOLI ,  Carmine CAPPETTA ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Saumya SUNEJA

IPC: G06N3/04 ,  G06N3/063 ,  G06F16/22 ,  G06N3/08 ,  G06K9/62

Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

公开(公告)号：US20210192833A1

公开(公告)日：2021-06-24

申请号：US17194055

申请日：2021-03-05

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06T15/08 ,  G06T7/62 ,  G06T7/11 ,  G06F16/901 ,  G06F9/38 ,  G06K9/00 ,  G06K9/62 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

公开(公告)号：US20210072894A1

公开(公告)日：2021-03-11

申请号：US17012501

申请日：2020-09-04

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20200310761A1

公开(公告)日：2020-10-01

申请号：US16833340

申请日：2020-03-27

Applicant: STMICROELECTRONICS S.R.L. ,  STMicroelectronics International N.V.

Inventor： Michele ROSSI ,  Giuseppe DESOLI ,  Thomas BOESCH ,  Carmine CAPPETTA

IPC: G06F7/72 ,  H03M7/18

Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.