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公开(公告)号：US20150062124A1
公开(公告)日：2015-03-05
申请号：US14321309
申请日：2014-07-01
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Usame Ceylan
CPC classification number: G06T15/005 , G06T1/20 , G06T1/60 , G06T11/001 , G06T11/203 , G06T11/40 , G06T15/04 , G06T15/80 , G09G5/363
Abstract: In an example rendering graphics data includes determining a stencil parameter that indicates a sampling rate for determining a coverage value for each antialiased pixel of a path of an image, determining, separately from the stencil parameter, a render target parameter that indicates a memory allocation for each antialiased pixel of the path, and rendering the path using the stencil parameter and the render target parameter.
Abstract translation: 在绘制图形数据的示例中，包括确定指出用于确定图像的路径的每个抗锯齿像素的覆盖值的采样率的模板参数，与模板参数分开地确定指示存储器分配的渲染目标参数 路径的每个抗锯齿像素，并使用模板参数和渲染目标参数渲染路径。
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公开(公告)号：US20140204080A1
公开(公告)日：2014-07-24
申请号：US14160324
申请日：2014-01-21
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Andrew Evan Gruber
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005
Abstract: A graphics processing unit (GPU) includes an indexed streamout buffer. The indexed streamout buffer is configured to: receive vertex data of a primitive, and determine if any entries in a reuse table of the indexed streamout buffer reference the vertex data. Responsive to determining that an entry of in the reuse table references the vertex data, the buffer is further configured to: generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table. Responsive to determining that an entry does not reference the vertex data, the indexed streamout buffer is configured to: store the vertex data in the buffer, generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table.
Abstract translation: 图形处理单元（GPU）包括索引流出缓冲器。 索引的流出缓冲器被配置为：接收原语的顶点数据，并且确定索引的流出缓冲器的重用表中的任何条目是否引用顶点数据。 响应于确定所述重用表中的条目引用所述顶点数据，所述缓冲器还被配置为：生成引用所述顶点数据的索引，将所述索引存储在所述缓冲器中，并且存储对所述重用表中的所述索引的引用 。 响应于确定条目不引用顶点数据，索引流出缓冲器被配置为：将顶点数据存储在缓冲器中，生成引用顶点数据的索引，将索引存储在缓冲器中，并存储引用 重用表中的索引。
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公开(公告)号：US20130265309A1
公开(公告)日：2013-10-10
申请号：US13830145
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Vineet Goel , Andrew Evan Gruber , Donghyun Kim
IPC: G06T15/80
CPC classification number: G06T15/80 , G06T15/00 , G06T15/005
Abstract: Aspects of this disclosure generally relate to a process for rendering graphics that includes performing, with a hardware shading unit of a graphics processing unit (GPU) designated for vertex shading, vertex shading operations to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit is configured to receive a single vertex as an input and generate a single vertex as an output. The process also includes performing, with the hardware shading unit of the GPU, a geometry shading operation to generate one or more new vertices based on one or more of the vertex shaded vertices, wherein the geometry shading operation operates on at least one of the one or more vertex shaded vertices to output the one or more new vertices.
Abstract translation: 本公开的方面通常涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件阴影单元执行遮蔽输入顶点的顶点着色操作，以便输出顶点着色顶点，其中 硬件单元被配置为接收单个顶点作为输入并且生成单个顶点作为输出。 该过程还包括利用GPU的硬件着色单元执行基于顶点着色顶点中的一个或多个以生成一个或多个新顶点的几何阴影操作，其中，几何阴影操作对一个 或多个顶点着色顶点，以输出一个或多个新顶点。
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公开(公告)号：US10559123B2
公开(公告)日：2020-02-11
申请号：US13829900
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Andrew Evan Gruber
Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes designating a hardware shading unit of a graphics processing unit (GPU) to perform first shading operations associated with a first shader stage of a rendering pipeline. The process also includes switching operational modes of the hardware shading unit upon completion of the first shading operations. The process also includes performing, with the hardware shading unit of the GPU designated to perform the first shading operations, second shading operations associated with a second, different shader stage of the rendering pipeline.
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公开(公告)号：US10210593B2
公开(公告)日：2019-02-19
申请号：US15009605
申请日：2016-01-28
Applicant: QUALCOMM Incorporated
Inventor： Anirudh Rajendra Acharya , Alexei Vladimirovich Bourd , David Rigel Garcia Garcia , Milind Nilkanth Nemlekar , Vineet Goel
Abstract: A graphics processing unit (GPU) may dispatch a first set of commands for execution on one or more processing units of the GPU. The GPU may receive notification from a host device indicating that a second set of commands are ready to execute on the GPU. In response, the GPU may issue a first preemption command at a first preemption granularity to the one or more processing units. In response to the GPU failing to preempt execution of the first set of commands within an elapsed time period after issuing the first preemption command, the GPU may issue a second preemption command at a second preemption granularity to the one or more processing units, where the second preemption granularity is finer-grained than the first preemption granularity.
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Patent Agency Ranking
公开(公告)号：US20180293761A1
公开(公告)日：2018-10-11
申请号：US16006502
申请日：2018-06-12
Applicant: QUALCOMM Incorporated
Inventor： Usame Ceylan , Vineet Goel , Juraj Obert , Liang Li
CPC classification number: G06T11/001 , G06T15/005
Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
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公开(公告)号：US09842376B2
公开(公告)日：2017-12-12
申请号：US15013714
申请日：2016-02-02
Applicant: QUALCOMM Incorporated
Inventor： Anirudh Rajendra Acharya , Gang Zhong , Vineet Goel
Abstract: Techniques are described with respect to preemption in which a graphics processing unit (GPU) may execute a first set of commands in response to receiving a draw call, the draw call defining a plurality of primitives that are to be rendered by the first set of commands, receive a preemption notification during execution of the first set of commands, and preempt the execution of the first set of commands, prior to completing the execution of the first set of commands to render the plurality of primitives of the draw call, for executing a second set of commands.
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公开(公告)号：US09805495B2
公开(公告)日：2017-10-31
申请号：US15054717
申请日：2016-02-26
Applicant: QUALCOMM Incorporated
Inventor： Juraj Obert , Tao Wang , Vineet Goel
CPC classification number: G06T15/005 , G06T15/06 , G06T2200/28 , G06T2210/21
Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
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公开(公告)号：US20170293995A1
公开(公告)日：2017-10-12
申请号：US15434851
申请日：2017-02-16
Applicant: QUALCOMM Incorporated
Inventor： Skyler Jonathon Saleh , Vineet Goel , Maurice Franklin Ribble , Andrew Evan Gruber
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/36
Abstract: A graphics processing unit (GPU) may rasterize a primitive into a plurality of samples, wherein vertices of the primitive are associated with VRS parameters. The GPU may determine a VRS quality group that comprises one or more sub regions of the plurality of samples based at least in part on the VRS parameters. The GPU may fragment shade a VRS tile that represents the VRS quality group, wherein the VRS tile comprises fewer samples than the VRS quality group. The GPU may amplify the stored VRS tile into shaded fragments that correspond to the VRS quality group.
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公开(公告)号：US20170263039A1
公开(公告)日：2017-09-14
申请号：US15066584
申请日：2016-03-10
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Ruijin Wu , Young In Yeo
CPC classification number: G06T15/005 , G06T15/00 , G06T15/20 , G06T15/205 , G06T19/20 , G06T2200/04
Abstract: In an example, a method for rendering a 3-D scene of graphical data into a 2-D scene may include dividing 2-D space used to represent the 3-D scene from a viewpoint into a plurality of tiles. The 3-D scene may include a plurality of primitives. The method may include generating visibility information for a first tile of the plurality of tiles. The method may include modifying the visibility information for the first tile to generate modified visibility information for the first tile. The method may include generating the 2-D scene using the modified visibility information for the first tile.
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