公开(公告)号：US20150264369A1

公开(公告)日：2015-09-17

申请号：US14656447

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan RAMASUBRAMONIAN ,  Fnu HENDRY ,  Ye-Kui WANG

IPC: H04N19/31 ,  H04N19/187 ,  H04N19/136 ,  H04N19/184

CPC classification number: H04N19/31 ,  H04N19/136 ,  H04N19/184 ,  H04N19/187 ,  H04N19/30 ,  H04N19/70

Abstract: An apparatus configured to code video information in a bitstream includes a memory and a processor in communication with the memory. The memory is configured to store video information associated with a video layer having a current picture. The processor is configured to: determine whether a slice segment header extension associated with the current picture is present in the bitstream; and determine that one or more most significant bits (MSBs) of a picture order count (POC) value associated with the current picture are not present in the bitstream in response to a determination that the slice segment header extension associated with the current picture is not present in the bitstream. The processor may encode or decode the video information in the bitstream.

Abstract translation: 被配置为对位流中的视频信息进行编码的装置包括存储器和与存储器通信的处理器。 存储器被配置为存储与具有当前图片的视频层相关联的视频信息。 处理器被配置为：确定与当前图片相关联的片段标题扩展是否存在于比特流中; 并且确定与当前图片相关联的图片顺序计数（POC）值的一个或多个最高有效位（MSB）不响应于确定与当前图片相关联的片段标题扩展不在存在于比特流中 存在于比特流中。 处理器可以对比特流中的视频信息进行编码或解码。

公开(公告)号：US20150181233A1

公开(公告)日：2015-06-25

申请号：US14575788

申请日：2014-12-18

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan RAMASUBRAMONIAN ,  Fnu HENDRY ,  Ye-Kui WANG

IPC: H04N19/597 ,  H04N19/52

CPC classification number: H04N19/597 ,  H04N19/463 ,  H04N19/52 ,  H04N19/70

Abstract: An apparatus configured to code video information includes a memory unit and a processor in communication with the memory unit. The memory unit is configured to store video information associated with a first video layer having a current picture. The processor is configured to process a first offset associated with the current picture, the first offset indicating a difference between (a) most significant bits (MSBs) of a first picture order count (POC) of a previous picture in the first video layer that precedes the current picture in decoding order and (b) MSBs of a second POC of the current picture.

Abstract translation: 被配置为对视频信息进行编码的装置包括与存储器单元通信的存储器单元和处理器。 存储单元被配置为存储与具有当前图片的第一视频层相关联的视频信息。 处理器被配置为处理与当前图像相关联的第一偏移，第一偏移指示第一视频层中先前图像的第一图像顺序计数（POC）的（a）最高有效位（MSB）之间的差异， 在当前图片的解码顺序前面和（b）当前图片的第二个POC的MSB。

公开(公告)号：US20150103905A1

公开(公告)日：2015-04-16

申请号：US14513113

申请日：2014-10-13

Applicant: QUALCOMM Incorporated

Inventor： Krishnakanth RAPAKA ,  Ye-Kui WANG ,  Jianle CHEN ,  Marta KARCZEWICZ

IPC: H04N19/503 ,  H04N19/51 ,  H04N19/61 ,  H04N19/44 ,  H04N19/91

CPC classification number: H04N19/503 ,  H04N19/30 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61 ,  H04N19/70 ,  H04N19/91

Abstract: Systems and methods for separately defining and indicating inter-layer prediction dependencies for a first layer with respect to each of a number of enhancement layers associated with the first layer are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory unit configured to store a first picture associated with a first layer and enhancement layer pictures associated with a plurality of enhancement layers. The video encoder further comprises a processor in communication with the memory unit. The processor is configured to provide a separate indication for each of the enhancement layers that indicates whether the first picture can be used for inter-layer prediction of the enhancement layer picture in a respective enhancement layer.

Abstract translation: 这里描述了用于相对于与第一层相关联的多个增强层中的每一个分别定义和指示第一层的层间预测依赖性的系统和方法。 在本公开中描述的主题的一个方面提供了一种视频编码器，其包括被配置为存储与第一层相关联的第一画面的存储器单元和与多个增强层相关联的增强层画面。 视频编码器还包括与存储器单元通信的处理器。 处理器被配置为为每个增强层提供指示第一图像是否可以用于相应增强层中的增强层图像的层间预测的单独指示。

公开(公告)号：US20150016544A1

公开(公告)日：2015-01-15

申请号：US14329675

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ye-Kui WANG ,  Krishnakanth RAPAKA

IPC: H04N19/46 ,  H04N19/44

CPC classification number: H04N19/52 ,  H04N19/184 ,  H04N19/187 ,  H04N19/30 ,  H04N19/44 ,  H04N19/46 ,  H04N19/597 ,  H04N19/70

Abstract: An apparatus for coding video information according to certain aspects includes a memory and computing hardware. The memory is configured to store video information. The computing hardware is configured to process at least one of a first signal indicating whether at least one sublayer of one or more layer sets has bit rate information to signal or a second signal indicating whether at least one sublayer of the one or more layer sets has picture rate information to signal.

Abstract translation: 根据某些方面的用于编码视频信息的装置包括存储器和计算硬件。 存储器被配置为存储视频信息。 计算硬件被配置为处理指示一个或多个层集合的至少一个子层是否具有信号的比特率信息的第一信号中的至少一个或指示所述一个或多个层集合中的至少一个子层是否具有 图像速率信息到信号。

公开(公告)号：US20150016534A1

公开(公告)日：2015-01-15

申请号：US14329416

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ye-Kui WANG ,  Krishnakanth RAPAKA

IPC: H04N19/597 ,  H04N19/51

CPC classification number: H04N19/52 ,  H04N19/184 ,  H04N19/187 ,  H04N19/30 ,  H04N19/44 ,  H04N19/46 ,  H04N19/597 ,  H04N19/70

Abstract: An apparatus for encoding video information according to certain aspects includes a memory and computing hardware. The memory is configured to store video information. The computing hardware is configured to determine a bit depth of one or more view identifiers to signal, wherein each of the one or more view identifiers is associated with a layer to be encoded. The computing hardware is further configured to signal the bit depth of the one or more view identifiers in a bitstream.

Abstract translation: 根据某些方面的用于编码视频信息的装置包括存储器和计算硬件。 存储器被配置为存储视频信息。 计算硬件被配置为确定要信号的一个或多个视图标识符的位深度，其中一个或多个视图标识符中的每一个与要编码的层相关联。 计算硬件还被配置为用信号通知位流中的一个或多个视图标识符的位深度。

公开(公告)号：US20150016502A1

公开(公告)日：2015-01-15

申请号：US14329804

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Krishnakanth RAPAKA ,  Vadim SEREGIN ,  Jianle CHEN ,  Ye-Kui WANG ,  Marta KARCZEWICZ

IPC: H04N19/187 ,  H04N19/50

CPC classification number: H04N19/50 ,  H04N19/105 ,  H04N19/187 ,  H04N19/33 ,  H04N19/70

Abstract: An apparatus configured to code video information includes a memory unit and a processor in communication with the memory unit. The memory unit is configured to store video information associated with a current layer and an enhancement layer, the current layer having a current picture. The processor is configured to determine whether the current layer may be coded using information from the enhancement layer, determine whether the enhancement layer has an enhancement layer picture corresponding to the current picture, and in response to determining that the current layer may be coded using information from the enhancement layer and that the enhancement layer has an enhancement layer picture corresponding to the current picture, code the current picture based on the enhancement layer picture. The processor may encode or decode the video information.

Abstract translation: 被配置为对视频信息进行编码的装置包括与存储器单元通信的存储器单元和处理器。 存储器单元被配置为存储与当前层和增强层相关联的视频信息，当前层具有当前画面。 处理器被配置为确定是否可以使用来自增强层的信息对当前层进行编码，确定增强层是否具有与当前图像对应的增强层图像，以及响应于确定当前层可以使用信息进行编码 并且增强层具有与当前画面对应的增强层画面，基于增强层画面对当前画面进行编码。 处理器可以对视频信息进行编码或解码。

公开(公告)号：US20140294062A1

公开(公告)日：2014-10-02

申请号：US14227910

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Jianle CHEN ,  Xiang LI ,  Krishnakanth RAPAKA ,  Ye-Kui WANG ,  Marta KARCZEWICZ

IPC: H04N19/105 ,  H04N19/30 ,  H04N19/503 ,  H04N19/176

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/30 ,  H04N19/33 ,  H04N19/46 ,  H04N19/503 ,  H04N19/593 ,  H04N19/70

Abstract: In one implementation, an apparatus is provided for encoding or decoding video information. The apparatus comprises a memory unit configured to store reference layer pictures associated with a reference layer, an enhancement layer, or both. The apparatus further comprises a processor operationally coupled to the memory unit. In one embodiment, the processor is configured to restrict usage of at most one reference layer pictures that has been resampled as an inter-layer reference picture, and predict a current picture using inter-layer prediction and the inter-layer reference picture.

Abstract translation: 在一个实现中，提供了一种用于对视频信息进行编码或解码的装置。 该装置包括被配置为存储与参考层，增强层或两者相关联的参考层图像的存储单元。 该装置还包括可操作地耦合到存储器单元的处理器。 在一个实施例中，处理器被配置为限制已被重采样的至多一个参考层图像的使用作为层间参考图片，并且使用层间预测和层间参考图片来预测当前图像。

公开(公告)号：US20140086337A1

公开(公告)日：2014-03-27

申请号：US13964688

申请日：2013-08-12

Applicant: QUALCOMM Incorporated

Inventor： Ye-Kui WANG

IPC: H04N7/26

CPC classification number: H04N19/50 ,  H04N19/30 ,  H04N19/46 ,  H04N19/61 ,  H04N19/70

Abstract: In some examples, a video encoder includes multiple sequence parameter set (SPS) IDs in an SEI message, such that multiple active SPSs can be indicated to a video decoder. In some examples, a video decoder activates a video parameter set (VPS) and/or one or more SPSs through referencing an SEI message, e.g., based on the inclusion of the VPS ID and one or more SPS IDs in the SEI message. The SEI message may be, as examples, an active parameter sets SEI message or a buffering period SEI message.

公开(公告)号：US20140086336A1

公开(公告)日：2014-03-27

申请号：US13918041

申请日：2013-06-14

Applicant: Qualcomm Incorporated

Inventor： Ye-Kui WANG

IPC: H04N7/26

CPC classification number: H04N19/136 ,  H04N19/149 ,  H04N19/152 ,  H04N19/31 ,  H04N19/44 ,  H04N19/70

Abstract: A computing device selects, from among a set of hypothetical reference decoder (HRD) parameters in a video parameter set and a set of HRD parameters in a sequence parameter set, a set of HRD parameters applicable to a particular operation point of a bitstream. The computing device performs, based at least in part on the set of HRD parameters applicable to the particular operation point, an HRD operation on a bitstream subset associated with the particular operation point.

Abstract translation: 计算设备从视频参数组中的一组假设参考解码器（HRD）参数和序列参数集中的一组HRD参数中选择适用于比特流的特定操作点的一组HRD参数。 所述计算设备至少部分地基于适用于特定操作点的一组HRD参数执行与特定操作点相关联的比特流子集的HRD操作。

公开(公告)号：US20140016708A1

公开(公告)日：2014-01-16

申请号：US13802045

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Ye-Kui WANG

IPC: H04N7/26

CPC classification number: H04N19/50 ,  H04N19/31 ,  H04N19/46 ,  H04N19/573 ,  H04N19/70

Abstract: In one example, a device for presenting video data includes a processor configured to determine an integer value for the video data, determine a difference value between a presentation time of a first picture and a presentation time of a second picture, wherein the difference value is equal to the integer value multiplied by a clock tick value, and present the first picture and the second picture according to the determined difference value.

Abstract translation: 在一个示例中，用于呈现视频数据的设备包括被配置为确定视频数据的整数值的处理器，确定第一画面的呈现时间与第二画面的呈现时间之间的差值，其中差值为 等于整数值乘以时钟刻度值，并根据确定的差值呈现第一图像和第二图像。