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公开(公告)号：US20230125544A1
公开(公告)日：2023-04-27
申请号：US17983213
申请日：2022-11-08
发明人： Alan J. Wilson , Donald M. Morgan
摘要： Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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公开(公告)号：US20220091978A1
公开(公告)日：2022-03-24
申请号：US17488190
申请日：2021-09-28
摘要： Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.
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公开(公告)号：US20200265912A1
公开(公告)日：2020-08-20
申请号：US16805049
申请日：2020-02-28
摘要： Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
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公开(公告)号：US20190333601A1
公开(公告)日：2019-10-31
申请号：US16505271
申请日：2019-07-08
发明人： Alan J. Wilson , John E. Riley
摘要： Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.
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公开(公告)号：US20170098480A1
公开(公告)日：2017-04-06
申请号：US15382394
申请日：2016-12-16
发明人： Alan J. Wilson , Jeffrey Wright
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
摘要： Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
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公开(公告)号：US09558851B2
公开(公告)日：2017-01-31
申请号：US15133096
申请日：2016-04-19
发明人： Alan J. Wilson , Jeffrey Wright
IPC分类号： G11C7/00 , G11C29/00 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C11/408 , G11C29/44
CPC分类号： G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
摘要： Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
摘要翻译： 公开了软包装修复的装置和方法。 一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。 匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的检测地址数据相匹配的匹配信号。 解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配 。 存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。
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公开(公告)号：US20160232987A1
公开(公告)日：2016-08-11
申请号：US15133096
申请日：2016-04-19
发明人： Alan J. Wilson , Jeffrey Wright
IPC分类号： G11C29/00 , G11C29/04 , G11C11/408
CPC分类号： G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
摘要： Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
摘要翻译： 公开了软包装修复的装置和方法。 一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。 匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的检测地址数据相匹配的匹配信号。 解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配 。 存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。
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公开(公告)号：US20150135038A1
公开(公告)日：2015-05-14
申请号：US14077630
申请日：2013-11-12
发明人： Alan J. Wilson , Jeffrey Wright
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C8/06 , G11C29/789 , G11C29/802 , G11C2029/4402
摘要： Apparatuses and methods for post package repair are disclosed. An apparatus can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells.
摘要翻译： 公开了用于后包装修复的装置和方法。 装置可以包括封装中的存储器单元。 存储元件可以存储响应于被激活的封装后修复模式的信息。 信息可以标识映射到要修复的存储器单元的一部分的地址。 存储元件可以响应于从包的节点接收的数据来存储信息。 行走令牌电路可以响应于被激活的封装后修复模式，以串行方式询问存储在存储元件中的信息。 映射电路可以根据询问将要修复的地址重新映射到存储器单元的另一部分。
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公开(公告)号：US12086449B1
公开(公告)日：2024-09-10
申请号：US17983213
申请日：2022-11-08
发明人： Alan J. Wilson , Donald M. Morgan
CPC分类号： G06F3/0647 , G06F3/0616 , G06F3/0659 , G06F3/0673 , G06F12/10 , G06F2212/657
摘要： Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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公开(公告)号：US20230350574A1
公开(公告)日：2023-11-02
申请号：US17731100
申请日：2022-04-27
发明人： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F3/0676
摘要： Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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