公开(公告)号：US20230215982A1

公开(公告)日：2023-07-06

申请号：US18093700

申请日：2023-01-05

Applicant: LG ELECTRONICS INC. ,  LG Display Co., Ltd.

Inventor： Sunyong SONG ,  Wonseok CHOI ,  Jeonghyo KWON ,  Junoh SHIN ,  Youngdo KIM

IPC: H01L33/38 ,  H01L33/62

CPC classification number: H01L33/382 ,  H01L33/62

Abstract: Discussed is a display device including a semiconductor light emitting device. A display device can include a substrate, first assembly electrodes, second assembly electrodes and the first assembly electrodes spaced apart from each other on the substrate, an insulating layer disposed on the second assembly electrode, an assembly barrier wall including a predetermined assembly hole and disposed on the insulating layer, a plating layer electrically connected to the first assembly electrode and the second assembly electrode, and a semiconductor light emitting device disposed in the assembly hole and electrically connected to the first assembly electrode and the second assembly electrode by the plating layer.

公开(公告)号：US20230023582A1

公开(公告)日：2023-01-26

申请号：US17786666

申请日：2020-01-08

Applicant: LG ELECTRONICS INC.

Inventor： Sungmin PARK ,  Wonseok CHOI ,  Soohyun KIM

IPC: H01L27/12 ,  H01L25/16 ,  H01L33/38

Abstract: A display device can include a base part, a semiconductor light emitting device disposed on a first region of the base part, and a plurality of assembly electrodes extending along one direction on the base part and to which a voltage is applied to dispose the semiconductor light emitting device at a pre-set position on the first region. The plurality of assembly electrodes are disposed not to overlap a thin film transistor.

公开(公告)号：US20180342633A1

公开(公告)日：2018-11-29

申请号：US15988478

申请日：2018-05-24

Applicant: LG ELECTRONICS INC.

Inventor： Wonseok CHOI ,  Gunho KIM

IPC: H01L31/0304 ,  H01L31/0224

Abstract: There is provided a compound semiconductor solar cell, comprising: a top cell including a compound semiconductor layer; a front electrode located on a front surface of the top cell and including a plurality of finger electrodes; and a back electrode disposed on a back surface of the top cell, wherein the top cell including a first window layer positioned on a light receiving surface of the top cell, a first base layer containing impurities of a first conductive type and located on a back surface of the first window layer, and a first emitter layer containing impurities of a second conductive type opposite the first conductive type and located on a back surface of the first base layer to form a p-n junction with the first base layer, wherein the first base layer includes a first layer having a first electrical conductivity and a second layer having a second electrical conductivity different from the first electrical conductivity, and wherein an interval between the second layer and the first emitter layer is larger than an interval between the first layer and the first emitter layer. The second electrical conductivity of the second layer may be higher than the first electrical conductivity of the first layer.

公开(公告)号：US20170084759A1

公开(公告)日：2017-03-23

申请号：US15367811

申请日：2016-12-02

Applicant: LG ELECTRONICS INC.

Inventor： Wonseok CHOI ,  Kwangsun JI ,  Heonmin LEE ,  Hojung SYN ,  Junghoon CHOI ,  Hyunjin YANG

IPC: H01L31/0216 ,  H01L31/18 ,  H01L31/0288 ,  H01L31/068 ,  H01L31/0236

CPC classification number: H01L31/02167 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/022441 ,  H01L31/02366 ,  H01L31/0288 ,  H01L31/03529 ,  H01L31/0368 ,  H01L31/0376 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/072 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/547

Abstract: A solar cell is discussed. The solar cell includes a silicon substrate; a front passivation layer positioned on a front surface of the silicon substrate; an n-doped layer positioned on the front surface of the silicon substrate; an anti-reflection layer positioned on the n-doped layer; a p-doped region positioned on a rear surface of the silicon substrate; an n-doped region positioned on the rear surface of the silicon substrate and spaced apart from the p-doped region; a rear passivation layer positioned on the rear surface of the silicon substrate, the rear passivation layer including: a first portion positioned between the p-doped region and the silicon substrate; a second portion positioned between the n-doped region and the silicon substrate, the second portion being space apart from the first potion; and a third portion disposed between the first portion and the second portion; a first electrode directly contacted to the p-doped region; and a second electrode directly contacted to the n-doped region.