公开(公告)号：US20070205928A1

公开(公告)日：2007-09-06

申请号：US11686807

申请日：2007-03-15

Applicant: Takeshi CHUJOH ,  Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Nagai

Inventor： Takeshi CHUJOH ,  Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Nagai

IPC: H03M7/40

CPC classification number: H04N19/69 ,  H04N19/152 ,  H04N19/159 ,  H04N19/176 ,  H04N19/187 ,  H04N19/37 ,  H04N19/46 ,  H04N19/52 ,  H04N19/61 ,  H04N19/65 ,  H04N19/66 ,  H04N19/70 ,  H04N19/89 ,  H04N19/93

Abstract: A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.

公开(公告)号：US20070160150A1

公开(公告)日：2007-07-12

申请号：US11716564

申请日：2007-03-12

Applicant: Takeshi Chujoh ,  Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Nagai

Inventor： Takeshi Chujoh ,  Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Nagai

IPC: H04N11/04

CPC classification number: H04N19/69 ,  H04N19/152 ,  H04N19/159 ,  H04N19/176 ,  H04N19/187 ,  H04N19/37 ,  H04N19/46 ,  H04N19/52 ,  H04N19/61 ,  H04N19/65 ,  H04N19/66 ,  H04N19/70 ,  H04N19/89 ,  H04N19/93

Abstract: A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.

公开(公告)号：US07215709B2

公开(公告)日：2007-05-08

申请号：US10971284

申请日：2004-10-25

Applicant: Noboru Yamaguchi ,  Toshiaki Watanabe ,  Takashi Ida ,  Yoshihiro Kikuchi

Inventor： Noboru Yamaguchi ,  Toshiaki Watanabe ,  Takashi Ida ,  Yoshihiro Kikuchi

IPC: H04B1/66

CPC classification number: H04N19/59 ,  H04N19/20

Abstract: An alpha-map encoding apparatus includes a first down-sampling circuit (21) for down-sampling an alpha-map signal which represents the shape of an object and the position in the frame of the object at a down-sampling ratio based on size conversion ratio information, an up-sampling circuit (23) for up-sampling the alpha-map signal at an up-sampling ratio based on size conversion ratio information given to restore the down-sampled alpha-map signal to an original size, and outputting a local decoded alpha-map signal, a motion estimation/compensation circuit (25) for generating a motion estimation/compensation signal on the basis of the previous decoded video signal and a motion vector signal, a second down-sampling circuit (26) for down-sampling the motion estimation/compensation signal at the down-sampling ratio, a binary image encoder for encoding the alpha-map signal down-sampled by the first down-sampling circuit to a binary image in accordance with the motion estimation/compensation signal down-sampled by the second down-sampling circuit, and outputting an encoded binary image signal, and a multiplexer for multiplexing and outputting the encoded binary image signal and the up-sampling ratio information.

Abstract translation: 阿尔法 - 地图编码装置包括：第一下采样电路（21），用于以基于尺寸的下采样比下降采样表示对象的形状和对象的帧中的位置的阿尔法 - 转换比信息，上采样电路（23），用于基于给定的大小转换比率信息以上取样比对上述阿尔法 - 映射信号进行上采样以将下采样的阿尔法 - 映射信号恢复到原始大小;以及 输出局部解码的阿尔法 - 映射信号，基于先前解码的视频信号和运动矢量信号产生运动估计/补偿信号的运动估计/补偿电路（25），第二下采样电路（26） 用于以下采样比对运动估计/补偿信号进行下采样的二进制图像编码器，用于根据运动估计/运算将由第一下采样电路下采样的阿尔法 - 映射信号编码为二进制图像 由第二下采样电路进行下采样的信号信号，并输出编码的二进制图像信号，以及多路复用器，用于复用并输出编码的二进制图像信号和上采样比信息。

公开(公告)号：US20070035568A1

公开(公告)日：2007-02-15

申请号：US11502190

申请日：2006-08-09

Applicant: Toshiaki Watanabe

Inventor： Toshiaki Watanabe

IPC: B41J29/38

CPC classification number: B41J2/04596 ,  B41J2/04581 ,  B41J2/04588 ,  B41J2202/10

Abstract: The objective of the present invention is to provide an ink jet head drive method whereby the same ink discharge speed is obtained, regardless of the locations of the ink chambers that discharge ink. A second drive pulse signal having a voltage value or a pulse width at which the discharge of ink does not occur is transmitted to an actuator, at the least, provided for an ink chamber, for which the discharge of ink is enabled, that is opposite a non-print area of a recording medium adjacent to a print area.

Abstract translation: 本发明的目的是提供一种喷墨头驱动方法，由此可以获得与排出墨水的墨水室的位置相同的排墨速度。 具有没有发生墨水排放的电压值或脉冲宽度的第二驱动脉冲信号至少被提供给致动器，该驱动脉冲信号至少提供用于允许墨水排出的墨室，这是相反的 与打印区域相邻的记录介质的非打印区域。

公开(公告)号：US20060200725A1

公开(公告)日：2006-09-07

申请号：US11402935

申请日：2006-04-13

Applicant: Yoshihiro Kikuchi ,  Toshiaki Watanabe ,  Kenshi Dachiku ,  Takeshi Chujoh ,  Takeshi Nagai

Inventor： Yoshihiro Kikuchi ,  Toshiaki Watanabe ,  Kenshi Dachiku ,  Takeshi Chujoh ,  Takeshi Nagai

IPC: H03M13/00

CPC classification number: H03M13/27 ,  G11B20/1813 ,  G11B27/3027 ,  H03M13/33 ,  H03M13/356 ,  H04J3/0602 ,  H04J3/0605 ,  H04J3/07 ,  H04L1/004 ,  H04L1/0041 ,  H04L1/0046 ,  H04L1/0072 ,  H04L1/0083 ,  H04L7/041 ,  H04L7/048 ,  H04L2001/0098 ,  H04N7/56 ,  H04N19/00 ,  H04N19/61 ,  H04N19/70 ,  H04N19/89 ,  H04N21/2383 ,  H04N21/4382

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

公开(公告)号：US07093170B2

公开(公告)日：2006-08-15

申请号：US10279109

申请日：2002-10-24

Applicant: Yoshihiro Kikuchi ,  Toshiaki Watanabe ,  Kenshi Dachiku ,  Takeshi Chujoh ,  Takeshi Nagai

Inventor： Yoshihiro Kikuchi ,  Toshiaki Watanabe ,  Kenshi Dachiku ,  Takeshi Chujoh ,  Takeshi Nagai

IPC: H04N7/52

CPC classification number: H03M13/27 ,  G11B20/1813 ,  G11B27/3027 ,  H03M13/33 ,  H03M13/356 ,  H04J3/0602 ,  H04J3/0605 ,  H04J3/07 ,  H04L1/004 ,  H04L1/0041 ,  H04L1/0046 ,  H04L1/0072 ,  H04L1/0083 ,  H04L7/041 ,  H04L7/048 ,  H04L2001/0098 ,  H04N7/56 ,  H04N19/00 ,  H04N19/61 ,  H04N19/70 ,  H04N19/89 ,  H04N21/2383 ,  H04N21/4382

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

公开(公告)号：US07051248B2

公开(公告)日：2006-05-23

申请号：US10278850

申请日：2002-10-24

Applicant: Yoshihiro Kikuchi ,  Toshiaki Watanabe ,  Kenshi Dachiku ,  Takeshi Chujoh ,  Takeshi Nagai

Inventor： Yoshihiro Kikuchi ,  Toshiaki Watanabe ,  Kenshi Dachiku ,  Takeshi Chujoh ,  Takeshi Nagai

IPC: H04L7/00

CPC classification number: H03M13/27 ,  G11B20/1813 ,  G11B27/3027 ,  H03M13/33 ,  H03M13/356 ,  H04J3/0602 ,  H04J3/0605 ,  H04J3/07 ,  H04L1/004 ,  H04L1/0041 ,  H04L1/0046 ,  H04L1/0072 ,  H04L1/0083 ,  H04L7/041 ,  H04L7/048 ,  H04L2001/0098 ,  H04N7/56 ,  H04N19/00 ,  H04N19/61 ,  H04N19/70 ,  H04N19/89 ,  H04N21/2383 ,  H04N21/4382

Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

公开(公告)号：US07020171B2

公开(公告)日：2006-03-28

申请号：US10432818

申请日：2002-03-28

Applicant: Toshiki Koshimae ,  Toshiaki Watanabe

Inventor： Toshiki Koshimae ,  Toshiaki Watanabe

IPC: H01S3/00 ,  H01S3/13

CPC classification number: H01S3/1312 ,  H01S3/0912

Abstract: A laser oscillator that, in accordance with a laser output instruction value or a current instruction value that is input, excites a laser medium and obtains a desired laser output comprises: reference waveform generation unit for employing the laser output instruction value or the current instruction value to generate a laser output waveform and a current waveform, which are references; a first comparison unit for obtaining, as a current monitor value, a current value used to excite the laser medium, and for comparing the current value with the current wave form generated by the reference wave form generation unit; and a second comparison unit for fetching, as a laser output monitor value, the value of a laser that is output by exciting the laser medium, and for comparing the value for the laser with the laser output waveform generated by the reference waveform generation unit, wherein an abnormality is detected.

Abstract translation: 激光振荡器，其根据激光输出指令值或输入的当前指令值激励激光介质并获得期望的激光输出包括：用于采用激光输出指令值或当前指令值的参考波形生成单元 产生作为参考的激光输出波形和电流波形; 第一比较单元，用于获得用于激励激光介质的当前值作为当前监视值，并将当前值与由参考波形生成单元生成的当前波形进行比较; 以及第二比较单元，用于将通过激励激光介质输出的激光的值作为激光输出监视值进行获取，并且用于将激光的值与由参考波形生成单元生成的激光输出波形进行比较， 其中检测到异常。

公开(公告)号：US07002999B2

公开(公告)日：2006-02-21

申请号：US10319506

申请日：2002-12-16

Applicant: Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Chujoh ,  Takeshi Nagai

Inventor： Toshiaki Watanabe ,  Yoshihiro Kikuchi ,  Takeshi Chujoh ,  Takeshi Nagai

IPC: H04J3/12

CPC classification number: H04N21/4382 ,  H04L1/0041 ,  H04L1/0072 ,  H04L1/0075 ,  H04N7/52 ,  H04N19/65 ,  H04N19/66 ,  H04N19/68 ,  H04N19/69 ,  H04N19/70 ,  H04N19/89 ,  H04N21/235 ,  H04N21/2368 ,  H04N21/242 ,  H04N21/4302 ,  H04N21/4341 ,  H04N21/435 ,  H04N21/4425 ,  H04N21/84 ,  H04N21/8455

Abstract: In an information transmission method, error robustness is provided for the bit stream itself so that decoding processing can be properly performed even in the event of an error in important information such as header information. A bit stream reconstruction circuit (107) in an encoding apparatus adds sync signals to the heads of encoded data streams, which are encoded by an encoder (103), in certain bit stream units, and then inserts designation information in each bit stream by using a designation information insertion circuit (106). Each designation information indicates the addition of information for reconstructing important header information. By inserting the designation information in the bit stream obtained, reconstruction information can be added to the bit stream. Even if, therefore, an error is introduced into the header information, and the information cannot be used for decoding processing, the decoding processing can be properly continued by using the new reconstruction information designated by the designation information as a substitute.

Abstract translation: 在信息传输方法中，为比特流本身提供错误鲁棒性，使得即使在诸如标题信息的重要信息中的错误的情况下也可以适当地执行解码处理。 编码装置中的比特流重构电路（107）将某些比特流单元将同步信号加到由编码器（103）编码的编码数据流的头部，然后使用 指定信息插入电路（106）。 每个指定信息指示用于重建重要标题信息的信息的添加。 通过将指定信息插入到获得的比特流中，可以将重构信息添加到比特流中。 因此，即使在标题信息中引入错误，并且信息不能用于解码处理，因此可以通过使用由指定信息指定的新的重建信息作为替代来适当地继续解码处理。

公开(公告)号：US06961471B2

公开(公告)日：2005-11-01

申请号：US10972538

申请日：2004-10-26

Applicant: Noboru Yamaguchi ,  Toshiaki Watanabe ,  Takashi Ida ,  Takaaki Kuratate

Inventor： Noboru Yamaguchi ,  Toshiaki Watanabe ,  Takashi Ida ,  Takaaki Kuratate

IPC: G06T3/40 ,  H04N7/26 ,  H04N7/46 ,  G06K9/36

CPC classification number: G06T3/4023 ,  G06T3/40 ,  H04N19/20 ,  H04N19/29 ,  H04N19/59

Abstract: A video encoding apparatus is provided with a resolution converting section, an encoding section, and a transmitting section. The resolution converting section enlarges or reduces a binary picture which represents the shape of an object. The encoding section encodes a binary picture reduced by the resolution converting section. The reduction ratio used by the resolution converting section is encoded, and the transmitting section transmits this encoded reduction ratio along with encoded data on the binary picture. The amount of encoded data produced from the encoding section is controlled by changing the enlargement/reduction ratio used by the resolution converting section.