公开(公告)号：US08577147B2

公开(公告)日：2013-11-05

申请号：US13150743

申请日：2011-06-01

Applicant: Shohei Hasegawa ,  Shinichi Eguchi ,  Hajime Kawashima ,  Koichi Kanamoto ,  Hiroki Inoue ,  Maki Yabuki ,  Katsutoshi Kobara

Inventor： Shohei Hasegawa ,  Shinichi Eguchi ,  Hajime Kawashima ,  Koichi Kanamoto ,  Hiroki Inoue ,  Maki Yabuki ,  Katsutoshi Kobara

IPC: G06K9/18 ,  G06K9/48

CPC classification number: G06K9/346 ,  G06K2209/01

Abstract: An objective is to eliminate dotted lines in a character box in image data to increase the character recognition rate. There are some cases in which a dotted line candidate cannot be extracted due to many overlapping parts of dotted lines and characters or due to a blurry part in a dotted line. In such cases, the position of a dotted line candidate is estimated referring to features such as the interval, length, width, etc. of a dotted line candidate in the same character box (or in a character box for another relevant item), and image data of the estimated position and image data of a previously extracted dotted line (or a reference dotted line) are compared to determine whether or not they are an identical dotted line.

Abstract translation: 目的是消除图像数据中字符框中的虚线，以增加字符识别率。 有些情况下，由于虚线和字符的重叠部分，或由于虚线中的模糊部分，虚线候选不能被提取。 在这种情况下，参照同一字符框（或另一相关项目的字符框）中的虚线候补的间隔，长度，宽度等特征来估计虚线候选的位置，以及 比较先前提取的虚线（或参考虚线）的估计位置和图像数据的图像数据，以确定它们是否是相同的虚线。

公开(公告)号：US08467231B2

公开(公告)日：2013-06-18

申请号：US13193756

申请日：2011-07-29

Applicant: Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

Inventor： Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C11/24

CPC classification number: G11C16/0408 ,  G11C11/405 ,  G11C16/02

Abstract: The semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error.

Abstract translation: 使用允许充分降低晶体管的截止电流的材料形成半导体器件; 例如，使用作为宽间隙半导体的氧化物半导体材料。 当使用允许充分降低晶体管的截止电流的半导体材料时，半导体器件可以长时间保存数据。 此外，信号线中的电位变化的定时相对于写入字线的电位变化的定时被延迟。 这使得可以防止数据写入错误。

公开(公告)号：US08435866B2

公开(公告)日：2013-05-07

申请号：US13256991

申请日：2010-09-28

Applicant: Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

Inventor： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

IPC: H01L21/306 ,  H01L21/304

CPC classification number: C30B29/36 ,  C30B33/06

Abstract: At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

Abstract translation: 制备至少一个具有背面并由碳化硅制成的单晶基板和具有主表面并由碳化硅制成的支撑部分。 在该制备步骤中，通过机械加工形成背面和主表面中的至少一个。 通过该形成步骤，在背面和主面中的至少一个上形成有晶体结构变形的表层。 表面层至少部分去除。 在该去除步骤之后，背面和主表面彼此连接。

公开(公告)号：US20120184113A1

公开(公告)日：2012-07-19

申请号：US13395793

申请日：2011-01-07

Applicant: Hiroki Inoue ,  Shin Harada ,  Makoto Sasaki ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa

Inventor： Hiroki Inoue ,  Shin Harada ,  Makoto Sasaki ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa

IPC: H01L21/30 ,  H05B3/02

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/7602 ,  H01L29/1608 ,  H01L29/66068

Abstract: A step of preparing a stack is performed to position each single-crystal substrate in a first single-crystal substrate group and a first base substrate face to face with each other, position each single-crystal substrate in a second single-crystal substrate group and a second base substrate face to face with each other, and stack the first single-crystal substrate group, the first base substrate, an insertion portion, the second single-crystal substrate group, and the second base substrate in one direction in this order. Next, the stack is heated so as to allow a temperature of the stack to reach a temperature at which silicon carbide can sublime and so as to form a temperature gradient in the stack with the temperature thereof getting increased in the above-described direction. In this way, silicon carbide substrates can be manufactured efficiently.

Abstract translation: 执行制备叠层的步骤，将第一单晶衬底组和第一衬底中的每个单晶衬底彼此面对，将每个单晶衬底放置在第二单晶衬底组中， 第二基板彼此面对，并且在一个方向上依次堆叠第一单晶基板组，第一基板，插入部，第二单晶基板组和第二基板。 接下来，对叠层进行加热，以使堆叠的温度达到碳化硅可以升华的温度，并且在上述方向上随着温度升高而在叠层中形成温度梯度。 以这种方式，可以有效地制造碳化硅衬底。

公开(公告)号：US20120161158A1

公开(公告)日：2012-06-28

申请号：US13394640

申请日：2011-06-17

Applicant: Tsutomu Hori ,  Shin Harada ,  Hiroki Inoue ,  Makoto Sasaki ,  Satomi Itoh ,  Kyoko Okita ,  Yasuo Namikawa

Inventor： Tsutomu Hori ,  Shin Harada ,  Hiroki Inoue ,  Makoto Sasaki ,  Satomi Itoh ,  Kyoko Okita ,  Yasuo Namikawa

IPC: H01L29/161

CPC classification number: H01L29/7802 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02631 ,  H01L21/0475 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

Abstract: A first silicon carbide substrate has a first backside surface connected to a supporting portion, a first front-side surface opposite to the first backside surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. A second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface opposite to the second backside surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A closing portion closes the gap. Thereby, foreign matters can be prevented from remaining in a gap between a plurality of silicon carbide substrates provided in a combined substrate.

Abstract translation: 第一碳化硅衬底具有连接到支撑部分的第一背面，与第一背面相对的第一前侧表面和将第一背面和第一前侧表面相互连接的第一侧表面。 第二碳化硅衬底具有连接到支撑部分的第二背面，与第二背面相对的第二前侧表面，以及将第二背面和第二前侧表面彼此连接的第二侧表面， 在第一侧表面和第二侧表面之间形成间隙。 闭合部分闭合间隙。 由此，可以防止异物残留在组合基板中设置的多个碳化硅基板之间的间隙中。

公开(公告)号：US20120063205A1

公开(公告)日：2012-03-15

申请号：US13230093

申请日：2011-09-12

Applicant: Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

Inventor： Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C11/24

CPC classification number: H01L27/1052 ,  G11C8/08 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4085 ,  G11C16/02 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C2211/4016

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

Abstract translation: 即使在不提供电力的情况下也可以保存存储的数据，并且没有限制写入操作的数量的半导体装置。 使用可以充分降低诸如作为宽间隙半导体的氧化物半导体材料的晶体管的截止电流的材料形成半导体器件。 当使用可以充分降低晶体管的截止电流的半导体材料时，半导体器件可以长期保存数据。 此外，通过提供电连接到写字线的电容器或噪声去除电路，可以减少或去除诸如短脉冲或输入到存储器单元的噪声的信号。 因此，可以防止当存储单元中的晶体管瞬间导通时擦除写入存储单元的数据的故障。

公开(公告)号：US20120056647A1

公开(公告)日：2012-03-08

申请号：US13221947

申请日：2011-08-31

Applicant: Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Kiyoshi Kato

Inventor： Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Kiyoshi Kato

IPC: H03K17/00

CPC classification number: G11C11/403 ,  G11C16/0433 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes a memory cell including a first transistor including a first channel formation region, a first gate electrode, and first source and drain regions; a second transistor including a second channel formation region provided so as to overlap with at least part of either of the first source region or the first drain region, a second source electrode, a second drain electrode electrically connected to the first gate electrode, and a second gate electrode; and an insulating layer provided between the first transistor and the second transistor. In a period during which the second transistor needs in an off state, at least when a positive potential is supplied to the first source region or the first drain region, a negative potential is supplied to the second gate electrode.

Abstract translation: 半导体器件包括存储单元，其包括第一晶体管，第一晶体管包括第一沟道形成区，第一栅电极以及第一源区和漏区; 第二晶体管，包括设置成与第一源极区域或第一漏极区域中的至少一部分重叠的第二沟道形成区域，第二源极电极，电连接到第一栅极电极的第二漏极电极，以及 第二栅电极; 以及设置在第一晶体管和第二晶体管之间的绝缘层。 在第二晶体管需要处于截止状态的期间中，至少当向第一源极区域或第一漏极区域提供正电位时，向第二栅电极提供负电位。

公开(公告)号：US20120033485A1

公开(公告)日：2012-02-09

申请号：US13193966

申请日：2011-07-29

Applicant: Takanori Matsuzaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Hiroki Inoue

Inventor： Takanori Matsuzaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C11/24

CPC classification number: G11C16/0408 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4087 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207

Abstract: In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.

Abstract translation: 在包括位线的m（m为3以上的自然数）字线，源极线，m条信号线，第1〜第m存储器单元和驱动电路的半导体器件中，所述存储单元包括 第一晶体管和第二晶体管，用于存储积聚在电容器中的电荷，第二晶体管包括形成在氧化物半导体层中的沟道。 在半导体装置中，驱动电路使用要输出到第j信号的信号，生成输出到第（j-1）（j为3以上的自然数）信号线的信号 线。

公开(公告)号：US20110233561A1

公开(公告)日：2011-09-29

申请号：US13073385

申请日：2011-03-28

Applicant: Taro NISHIGUCHI ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

Inventor： Taro NISHIGUCHI ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

IPC: H01L29/161

CPC classification number: H01L29/7802 ,  H01L21/0445 ,  H01L21/0475 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/6606 ,  H01L29/66068

Abstract: A supporting portion is made of silicon carbide. At least one layer has first and second surfaces. The first surface is supported by the supporting portion. The at least one layer has first and second regions. The first region is made of silicon carbide of a single-crystal structure. The second region is made of graphite. The second surface has a surface formed by the first region. The first surface has a surface formed by the first region, and a surface formed by the second region. In this way, a semiconductor substrate can be provided which has a region made of silicon carbide having a single-crystal structure and a supporting portion made of silicon carbide and allows for reduced electric resistance of an interface therebetween.

Abstract translation: 支撑部分由碳化硅制成。 至少一层具有第一和第二表面。 第一表面由支撑部分支撑。 所述至少一层具有第一和第二区域。 第一区域由单晶结构的碳化硅制成。 第二区域由石墨制成。 第二表面具有由第一区域形成的表面。 第一表面具有由第一区域形成的表面和由第二区域形成的表面。 以这种方式，可以提供具有由具有单晶结构的碳化硅制成的区域和由碳化硅制成的支撑部分的区域并且允许其之间的界面的电阻降低的半导体衬底。

公开(公告)号：US20110229037A1

公开(公告)日：2011-09-22

申请号：US13150743

申请日：2011-06-01

Applicant: Shohei Hasegawa ,  Shinichi Eguchi ,  Hajime Kawashima ,  Koichi Kanamoto ,  Hiroki Inoue ,  Maki Yabuki ,  Katsutoshi Kobara

Inventor： Shohei Hasegawa ,  Shinichi Eguchi ,  Hajime Kawashima ,  Koichi Kanamoto ,  Hiroki Inoue ,  Maki Yabuki ,  Katsutoshi Kobara

IPC: G06K9/18

CPC classification number: G06K9/346 ,  G06K2209/01

Abstract: An objective is to eliminate dotted lines in a character box in image data to increase the character recognition rate. There are some cases in which a dotted line candidate cannot be extracted due to many overlapping parts of dotted lines and characters or due to a blurry part in a dotted line. In such cases, the position of a dotted line candidate is estimated referring to features such as the interval, length, width, etc. of a dotted line candidate in the same character box (or in a character box for another relevant item), and image data of the estimated position and image data of a previously extracted dotted line (or a reference dotted line) are compared to determine whether or not they are an identical dotted line.

Abstract translation: 目的是消除图像数据中字符框中的虚线，以增加字符识别率。 有些情况下，由于虚线和字符的重叠部分，或由于虚线中的模糊部分，虚线候选不能被提取。 在这种情况下，参照同一字符框（或另一相关项目的字符框）中的虚线候补的间隔，长度，宽度等特征来估计虚线候选的位置，以及 比较先前提取的虚线（或参考虚线）的估计位置和图像数据的图像数据，以确定它们是否是相同的虚线。