LOGICAL MEMORY BUFFERS FOR A MEDIA CONTROLLER

    公开(公告)号:US20170329710A1

    公开(公告)日:2017-11-16

    申请号:US15155235

    申请日:2016-05-16

    CPC classification number: G06F13/1673 Y02D10/14

    Abstract: In some examples, a media controller includes a buffer and controller circuitry. The controller circuitry may receive, from a memory device linked to the media controller, an indication of a number of memory subunits that the memory device is divided into. The controller circuitry may also allocate, within the buffer, a number of logical memory buffers for the memory device greater than the number of memory subunits and indicate to a memory controller that a number of memory units accessible for the memory device is the number of logical memory buffers.

    COMMUNICATION IN A HETEROGENEOUS DISTRIBUTED SYSTEM
    32.
    发明申请
    COMMUNICATION IN A HETEROGENEOUS DISTRIBUTED SYSTEM 审中-公开
    异构分布系统中的通信

    公开(公告)号:US20170013060A1

    公开(公告)日:2017-01-12

    申请号:US15113976

    申请日:2014-01-31

    Abstract: Methods and systems for communication in a heterogeneous distributed system are described. The described systems implement the described methods, where the method includes receiving data from at least one data source, by a data store computing device. The method further includes identifying a data source from amongst the at least one data source to have generated the data, based on host parameters associated with the data source and the data. Further, the method includes determining the data to be represented in a first data presentation based on the identified data source and the host parameters and transforming the data from the first data presentation to a second data presentation, where the data store computing device operates using the second data presentation.

    Abstract translation: 描述了异构分布式系统中通信的方法和系统。 所描述的系统实现所描述的方法,其中该方法包括由数据存储计算设备从至少一个数据源接收数据。 该方法还包括基于与数据源和数据相关联的主机参数从至少一个数据源中识别数据源以生成数据。 此外,该方法包括基于所识别的数据源和主机参数确定要在第一数据呈现中表示的数据,并将数据从第一数据呈现转换为第二数据呈现,其中数据存储计算设备使用 第二次数据呈现。

    ACCESS CONTROLLED MEMORY REGION
    33.
    发明申请
    ACCESS CONTROLLED MEMORY REGION 审中-公开
    访问控制存储区

    公开(公告)号:US20160342534A1

    公开(公告)日:2016-11-24

    申请号:US15109334

    申请日:2014-01-30

    Abstract: A first component associated with an access controlled memory region receives a transaction request including a protocol header from a second component. The first component sends, to the second component, a negative acknowledgment in response to determining that the second component is not authorized to access the access controlled memory region, based on information in the protocol header.

    Abstract translation: 与访问控制的存储器区域相关联的第一组件从第二组件接收包括协议头部的事务请求。 基于协议头部中的信息,响应于确定第二组件未被授权访问访问受控存储器区域,第一组件向第二组件发送否定确认。

    Connector Assembly Including an Edge-Attachable Optical Connector Housing and Optical Connector

    公开(公告)号:US20200158969A1

    公开(公告)日:2020-05-21

    申请号:US16195085

    申请日:2018-11-19

    Abstract: An edge-attachable (EA) optical connector includes an optical connector housing for an optical connector. The optical connector housing includes a slot that aligns with a module board edge finger electrical connector, such that the optical connector housing can be slid over a module board edge finger electrical connector and attached to the module board edge. An optical connector on one end of an optical fiber bundle or ribbon fits within the optical connector housing. When the optical connector housing is attached to the module board edge, the optical connector blind mates with a host optical connector supported by a bracket to which a host electrical connector is attached. An optical connector on another end of the optical fiber bundle or ribbon mates with a module board optical connector. The module board optical connector may include an optical socket mounted on an opto-electronic chip disposed on the module board. The EA optical connector can be easily attached to the module board edge such that it fits around the host electrical connector to allow for optical connectivity in addition to electrical connectivity.

    Component multicast protocol
    38.
    发明授权

    公开(公告)号:US09992034B2

    公开(公告)日:2018-06-05

    申请号:US15116001

    申请日:2014-03-13

    CPC classification number: H04L12/1868 H04L1/16 H04L1/18 H04L12/1881

    Abstract: A method includes transmitting, from a first component of an electronic device, a first transaction associated with a first sequence number to a second component of the electronic device based on a multicast protocol. The first transaction is independent of an Internet protocol. The method also includes receiving an acknowledgement message that corresponds to a positive acknowledgment message or a negative acknowledgement message. The method further includes in response to receiving the negative acknowledgement message, retransmitting the first transaction to the second component using the first sequence number based on the multicast protocol.

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