公开(公告)号：US06271780B1

公开(公告)日：2001-08-07

申请号：US09168601

申请日：1998-10-08

Applicant: Xue-Mei Gong ,  Ka Yin Leung ,  Eric J. Swanson

Inventor： Xue-Mei Gong ,  Ka Yin Leung ,  Eric J. Swanson

IPC: H03H188

CPC classification number: H03M3/488 ,  H04R3/00

Abstract: A gain ranging AD converter is provided having two separate gain paths. There is provided a low-gain path and a high-gain path. The low gain path is processed through an analog modulator (333) and then through a filter section to provide on an output of a high-pass filter (339), a low-gain signal which is then compensated for in an equalizer section (347). This equalizing section (347) calibrates the output signal to ensure that the difference between the calibrated signal and the high-gain signal differs only by the fixed gain between the two paths. The high-gain path also includes a modulator (335) for processing through a filter section to provide on the output of a high-pass filter section (343) a high-gain signal. A calibration generator (361) is utilized to generate the parameters for performing the equalization. This calibration generator (361) utilizes both phase and amplitude information from the high-gain path and from both the calibrated low-gain path to generate the calibration parameters for use by the equalizing section (347). Thereafter, the mixing operation is performed to provide a “blend” before summing with a summing junction (351).

Abstract translation: 增益测距AD转换器具有两个独立的增益路径。 提供了低增益路径和高增益路径。 通过模拟调制器（333）处理低增益路径，然后通过滤波器部分提供高通滤波器（339）的输出，然后在均衡器部分（347）中对低增益信号进行补偿 ）。 该均衡部分（347）校准输出信号，以确保校准信号和高增益信号之间的差异仅仅在两条路径之间的固定增益之间不同。 高增益路径还包括用于通过滤波器部分处理以在高通滤波器部分（343）的输出上提供高增益信号的调制器（335）。 校准发生器（361）用于产生用于执行均衡的参数。 该校准发生器（361）利用来自高增益路径的相位和幅度信息以及来自校准的低增益路径的两个相位和幅度信息来生成用于均衡部分（347）的校准参数。 此后，执行混合操作以在与求和结（351）相加之前提供“混合”。

公开(公告)号：US5652585A

公开(公告)日：1997-07-29

申请号：US416618

申请日：1995-04-05

Applicant: Ka Yin Leung ,  Kafai Leung ,  Eric J. Swanson

Inventor： Ka Yin Leung ,  Kafai Leung ,  Eric J. Swanson

IPC: H03H17/02 ,  H03M3/02 ,  H03M3/04 ,  H03M7/00 ,  H03M1/12

CPC classification number: H03M7/3008 ,  H03H17/0286 ,  H03M3/462 ,  H03M7/3026 ,  H03M7/3042

Abstract: An analog-to-digital converter is comprised of an analog delta-sigma modulator (10) and a digital processing section (14). The digital processing section (14) is comprised of a plurality of digital processing sections fabricated on a monolithic device. A high precision FIR filter (20) is provided for providing a high resolution output on a bus (22). Additionally, a low group delay FIR filter (30) is provided to filter the data and provide an output with a much lower delay than that of the FIR filter (20). The output of filter (20) can either be processed through a high-pass filter (40) and/or through a noise shaping psycho-acoustic filter (36) to provide select outputs. These outputs are all input to the serial interface device (52), which is operable to select one of the outputs, that of the filter (30), that of the filter (20), or that of the output of the noise shaping filter (36) or that of the filter (40) for conversion to a serial data stream. Two serial data streams can be generated at the same time from different ones of the inputs. Configuration data can be input to various configuration registers through a data input port (58), this allowing selection of the different functions during the operation thereof.

Abstract translation: 模拟 - 数字转换器由模拟Δ-Σ调制器（10）和数字处理部分（14）组成。 数字处理部分（14）由在单片装置上制造的多个数字处理部分组成。 提供了一种用于在总线（22）上提供高分辨率输出的高精度FIR滤波器（20）。 此外，提供低群延迟FIR滤波器（30）以对数据进行滤波并提供具有比FIR滤波器（20）的延迟低得多的延迟的输出。 滤波器（20）的输出可以通过高通滤波器（40）和/或通过噪声整形心理声学滤波器（36）进行处理，以提供选择输出。 这些输出全部输入到串行接口设备（52），其可操作以选择滤波器（30），滤波器（20）的输出，噪声整形滤波器（20）的输出 （36）或滤波器（40）的输出端转换为串行数据流。 可以从不同的输入端同时生成两个串行数据流。 配置数据可以通过数据输入端口（58）输入到各种配置寄存器，这允许在其操作期间选择不同的功能。

公开(公告)号：US5247210A

公开(公告)日：1993-09-21

申请号：US737558

申请日：1991-07-26

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03F3/45 ,  H03K5/24

CPC classification number: H03F3/45479 ,  H03F3/45771 ,  H03K5/2481 ,  H03K5/249

Abstract: Method and circuitry for decreasing the recovery time of an MOS differential voltage comparator after an input voltage overdrive. At the beginning of a comparison cycle a reverse voltage is momentarily applied between the gates and sources of the input pair of source-coupled MOS transistors of sufficient magnitude to form a charge accumulation layer in the channel region of each of the transistors. Operating the differential voltage comparator in such manner substantially decreases the time required for the transistors to recover from an imbalance in their electrical characteristics caused by the input voltage overdrive.

Abstract translation: 在输入电压过驱动后，减小MOS差分电压比较器的恢复时间的方法和电路。 在比较周期开始时，反向电压瞬间施加在输入的一对源极耦合MOS晶体管的栅极和源极之间，以足以在每个晶体管的沟道区中形成电荷累积层。 以这种方式操作差分电压比较器大大减少了晶体管从由输入电压过驱动引起的电特性的不平衡恢复所需的时间。

公开(公告)号：US5079550A

公开(公告)日：1992-01-07

申请号：US428396

申请日：1989-10-27

Applicant: Navdeep S. Sooch ,  Donald A. Kerth ,  Bruce P. Del Signore ,  Eric J. Swanson

Inventor： Navdeep S. Sooch ,  Donald A. Kerth ,  Bruce P. Del Signore ,  Eric J. Swanson

IPC: H03M3/02

CPC classification number: H03M3/496 ,  H03M3/43 ,  H03M3/438

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.

Abstract translation: 过采样模数转换器包括具有作为连续时间积分器工作的第一积分器级的模拟环路滤波器。 第二，第三和第四积分器级是离散时间或采样积分器。 连续时间第一积分器提供环路滤波器所需的热噪声特性，而离散时间积分器级提供有利于模数转换器的整体运行的环路稳定性和传输特性。

公开(公告)号：US4746899A

公开(公告)日：1988-05-24

申请号：US916160

申请日：1986-10-07

Applicant: Eric J. Swanson ,  Navdeep S. Sooch ,  David J. Knapp

Inventor： Eric J. Swanson ,  Navdeep S. Sooch ,  David J. Knapp

IPC: H03M1/08 ,  H03M3/02

CPC classification number: H03M3/324 ,  H03M3/458

Abstract: Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.

Abstract translation: 用于减少模数转换器中电噪声的有害影响的方法，其中A / D转换器的模拟和数字电路都体现在相同的集成电路中。 该方法包括用第一时钟信号对模拟输入电压进行采样，产生相对于第一时钟信号被延迟的第二时钟信号，并且使用第二时钟信号作为数字电路的时钟。 根据本发明的另一方面，用于减少A / D转换器中的噪声影响的方法，其中这种噪声由数字抽取滤波器产生，包括同步流水线数字抽取滤波器的算术运算。

公开(公告)号：US4611130A

公开(公告)日：1986-09-09

申请号：US579772

申请日：1984-02-13

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03K5/24 ,  H03K17/16

CPC classification number: H03K5/249

Abstract: The present invention relates to a floating input comparator capable of mitigating the effects of parasitic capacitance present at the input stage of the comparator. In particular, the present invention functions to substantially reduce the effects of parasitic capacitive voltage division present at the nodes interrogated during each detection cycle. In accordance with the present invention, precharging devices (40, 42, 44) are coupled between a predetermined reference potential (VDD) and the affected nodes (D, E, C) to precharge the nodes to the full reference potential prior to each detection cycle, thereby eliminating the effects of a changing, unknown parasitic capacitance at these nodes by replacing an unknown parasitic potential with the known reference potential.

Abstract translation: 本发明涉及一种能够减轻存在于比较器的输入级的寄生电容的影响的浮动输入比较器。 特别地，本发明用于大大减少在每个检测周期期间询问的节点处存在的寄生电容电压分割的影响。 根据本发明，预充电装置（40,42,44）在预定参考电位（VDD）和受影响的节点（D，E，C）之间耦合，以在每次检测之前将节点预充电到全参考电位 循环，从而通过用已知的参考电位替换未知的寄生电位来消除在这些节点处的变化的未知寄生电容的影响。

公开(公告)号：US06950840B2

公开(公告)日：2005-09-27

申请号：US10832141

申请日：2004-04-26

Applicant: Edwin De Angel ,  Eric J. Swanson

Inventor： Edwin De Angel ,  Eric J. Swanson

IPC: G06F1/26 ,  G06F7/52 ,  G06F7/533 ,  G06J1/00

CPC classification number: G06F7/5336 ,  G06F2207/3868

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract translation: 用于乘法器系统的电路包括用于确定接近采样操作的计数器，以及用于在对称噪声不变操作和低功率操作模式之间进行选择的开关。 噪声不变电路禁用多行乘法器中的行跳跃操作，以启用模拟采样。 在模拟采样之前的几个数字周期的时间，完成禁止行跳过操作。 模拟采样完成后，省电倍增器行跳转恢复。

公开(公告)号：US06426713B1

公开(公告)日：2002-07-30

申请号：US09695708

申请日：2000-10-25

Applicant: Aryesh Amar ,  Edwin De Angel ,  Eric J. Swanson

Inventor： Aryesh Amar ,  Edwin De Angel ,  Eric J. Swanson

IPC: H03M106

CPC classification number: H03M1/1028 ,  H03M1/1225 ,  H03M3/38 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452 ,  H03M3/494

Abstract: In a signal processing integrated circuit having a plurality of physical channels and a plurality of gain registers, a plurality of offset registers and an plurality of setup registers, mechanisms are provided to assign one of a plurality of gain registers independently of a selected one of a plurality of offset registers when processing signals from a physical channel.

Abstract translation: 在具有多个物理信道和多个增益寄存器的信号处理集成电路中，提供多个偏移寄存器和多个建立寄存器机制，以分配多个增益寄存器中的一个独立于所选择的一个 当处理来自物理信道的信号时，多个偏移寄存器。

公开(公告)号：US06369740B1

公开(公告)日：2002-04-09

申请号：US09429001

申请日：1999-10-29

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03M112

CPC classification number: H03M1/208 ,  H03M1/185 ,  H03M1/187

Abstract: A programmable gain preamplifier is provided which has a low temperature drift and good dynamic range characteristics. The programmable gain preamplifier may be coupled to an analog to digital converter. The analog to digital converter may be a switched capacitor array analog to digital converter. The analog to digital converter may be a resistor array and capacitor array analog to digital converter. A resistor string having contacts out of the resistor string current path may be utilized with the programmable gain preamplifier or the analog to digital converter or both. The resistor string may be utilized to calibrate the analog to digital converter or the programmable gain preamplifier or both. The resistor string may also be utilized by the analog to digital converter when conversions are being performed. The programmable gain preamplifier provides a programmable gain of the difference between two input signals (Ain and Ain′ for example). One of the input signals (Ain′) may be an estimation of the other input signal (Ain).

Abstract translation: 提供了一种可编程增益前置放大器，具有低温度漂移和良好的动态范围特性。 可编程增益前置放大器可以耦合到模数转换器。 模数转换器可以是开关电容阵列模数转换器。 模数转换器可以是电阻阵列和电容阵列模数转换器。 具有电阻串电流路径之外的触点的电阻串可以与可编程增益前置放大器或模数转换器或二者一起使用。 电阻串可用于校准模数转换器或可编程增益前置放大器或两者。 当执行转换时，电阻串也可以由模数转换器利用。 可编程增益前置放大器提供两个输入信号（例如Ain和Ain'）之间差异的可编程增益。 输入信号（Ain'）中的一个可以是另一个输入信号（Ain）的估计。

公开(公告)号：US06292911B1

公开(公告)日：2001-09-18

申请号：US09215430

申请日：1998-12-17

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: G01R3128

CPC classification number: G06F11/1008 ,  G06F11/221

Abstract: A technique for detecting error when transferring data on a data channel between components disposed on the data channel. A test pattern is generated by a controller on the data channel and sent to a data storage component on the channel. The data storage component tests the received test pattern to determine if the pattern has been corrupted.

Abstract translation: 一种用于在数据信道上配置的组件之间传输数据信道上的数据时检测错误的技术。 测试模式由数据通道上的控制器生成并发送到通道上的数据存储组件。 数据存储组件测试接收到的测试模式以确定模式是否已损坏。