公开(公告)号：US06904511B2

公开(公告)日：2005-06-07

申请号：US10269373

申请日：2002-10-11

申请人： Erdem Hokenek ,  Mayan Moudgill ,  C. John Glossner

发明人： Erdem Hokenek ,  Mayan Moudgill ,  C. John Glossner

IPC分类号： G06F20060101 ,  G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F12/02 ,  G06F13/16 ,  G06F15/167

CPC分类号： G06F9/30123 ,  G06F9/3851

摘要： Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

摘要翻译： 公开了一种由多线程处理器进行基于线程的寄存器文件访问的技术。 多线程处理器确定与特定处理器线程相关联的线程标识符，并且利用线程标识符的至少一部分来选择由相应处理器线程访问的相关联的寄存器文件的特定部分。 在说明性实施例中，寄存器文件被划分为偶数和奇数部分，其中最小有效位或线程标识符的其他部分用于选择给定处理器线程使用的偶数或奇数部分。 基于线程的寄存器文件选择可以与令牌触发的线程和指令流水线结合使用。 有利地，本发明减少寄存器文件端口要求，从而减少处理器功耗，同时保持期望的并发级别。

公开(公告)号：US08819099B2

公开(公告)日：2014-08-26

申请号：US12442374

申请日：2007-09-24

申请人： Mihai Sima ,  Daniel Iancu ,  Hua Ye ,  Mayan Moudgill

发明人： Mihai Sima ,  Daniel Iancu ,  Hua Ye ,  Mayan Moudgill

IPC分类号： G06F7/32

CPC分类号： G06F17/16 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3895

摘要： A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

摘要翻译： 在无线通信设备中提供数字信号处理器，其中所述处理器包括向量单元，耦合到所述向量单元并由所述向量单元访问的第一和第二寄存器; 以及指令集，其被配置为通过使用向量单元和第一和第二寄存器的坐标旋转数字计算机指令来执行信道值矩阵的矩阵求逆。

公开(公告)号：US08732382B2

公开(公告)日：2014-05-20

申请号：US13057469

申请日：2009-08-05

申请人： Mayan Moudgill ,  Shenghong Wang

发明人： Mayan Moudgill ,  Shenghong Wang

IPC分类号： G06F12/00

CPC分类号： G06F13/28

摘要： A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

摘要翻译： 描述了用于DMA引擎的操作的方法。 启动复制以将第一数量的字节从第一源存储器位置传送到第一目的地存储器位置。 然后，在第一个字节数被复制之前发出停止指令。 复制停止后，建立第二个字节数，包含剩下的要复制的字节。 传输停止后，识别出第二个字节数量。 然后生成和存储数量信息。 识别第二源存储器位置以指示第二数量的字节存储在哪里。 然后生成并存储第二源存储器位置信息。 然后识别第二目的地存储器位置以指示要传送第二数量字节的位置。 然后生成并存储第二目的地存储器位置信息。

公开(公告)号：US08171265B2

公开(公告)日：2012-05-01

申请号：US12375202

申请日：2008-12-08

申请人： Mayan Moudgill ,  Sitij Agrawal

发明人： Mayan Moudgill ,  Sitij Agrawal

IPC分类号： G06F15/00 ,  G06F9/34

CPC分类号： G06F9/30018 ,  G06F9/345 ,  G06F9/355

摘要： A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2b bits, using selected b bits of the first index to select at least one target bit in the loaded second value, shifting the target bit into the bottom of the first index, and computing a second index based on the shifting of the target bit into the bottom of the first index. Other methods and variations are also described.

摘要翻译： 描述由处理器上的指令集执行的方法。 该方法包括提供tbbit指令，输入tbbit指令的第一索引，加载用于tbbit指令的第二值，其中使用所选择的第一索引的b位来选择至少一个目标，其中第二值包括至少2b位 将目标位移动到第一索引的底部，并且基于目标位移到第一索引的底部来计算第二索引。 还描述了其它方法和变型。

公开(公告)号：US20110241744A1

公开(公告)日：2011-10-06

申请号：US13061106

申请日：2009-08-20

申请人： Mayan Moudgill ,  Gary Nacer ,  Shenghong Wang

发明人： Mayan Moudgill ,  Gary Nacer ,  Shenghong Wang

IPC分类号： H03K3/289

CPC分类号： G06F9/30141 ,  G06F9/30116 ,  G06F9/30123

摘要： A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.

摘要翻译： 描述用于多线程处理器的处理器寄存器文件。 在一个实施例中，处理器寄存器文件包括具有N个b位宽寄存器的T线程。 每个寄存器包括一个b位主锁存器，连接到主锁存器的T b位从属锁存器和一个从锁存器写使能，连接到从锁存器。 主锁存器不会与从动锁存器同时打开。 此外，在任何给定时间只有一个从锁存器被使能。 对于本领域技术人员来说显而易见的是，T，N和b都是整数。 还提供了其它实施例和变型。

公开(公告)号：US20100241834A1

公开(公告)日：2010-09-23

申请号：US12740423

申请日：2008-08-28

申请人： Mayan Moudgill

发明人： Mayan Moudgill

IPC分类号： G06F9/30

CPC分类号： G06F9/30163 ,  G06F9/3016

摘要： The method selects registers by a register instruction field having x bits. A first group of registers has up to 2y registers and a second group of registers has up to 2z registers where y and z are at least one and not great than x. The method includes encoding an instruction field with x bits wherein y of the x bits designates a register of the first group and z bits of the x bits designates a register of the second group. The register of the first group designated by the y bits of the instruction field and the register of the second group designated by the z bits of the instruction field are selected.

摘要翻译： 该方法通过具有x位的寄存器指令字段来选择寄存器。 第一组寄存器具有最多2个寄存器，第二组寄存器具有高达2z寄存器，其中y和z至少为1，而不是x。 该方法包括用x位编码指令字段，其中x位的y指定第一组的寄存器，x位的z位指定第二组的寄存器。 选择由指令字段的y位指定的第一组的寄存器和由指令字段的z位指定的第二组的寄存器。

公开(公告)号：US07058117B1

公开(公告)日：2006-06-06

申请号：US10530439

申请日：2004-07-26

申请人： Daniel Iancu ,  John Glossner ,  Mayan Moudgill

发明人： Daniel Iancu ,  John Glossner ,  Mayan Moudgill

IPC分类号： H04B1/707

CPC分类号： H04B1/7107 ,  H04B1/7115 ,  H04B1/7117 ,  H04B1/712

摘要： A method of extracting data from a received signal including multi-path interference in a rake receiver. The method includes sampling and filtering the received signal; estimating a time delay τl between paths for the filtered samples ψ(τ); and estimating channel complex coefficient cl for the filtered samples ψ(τ). Transmitted data x(τl) is extracted from the filtered samples ψ(τ) for each path l by solutions of simultaneous equations of the following filtered samples ψ(τ) equation ψ ⁡ ( τ ) ⁢ R ff - 1 ⁡ ( τ k - τ ^ 0 ) ⁢ Λ ss H ⁡ ( τ ^ k ) = ∑ l = 0 N p + 1 ⁢ ⁢ c i ⁡ ( τ l ) × ( τ l ) ⁢ Λ ss ⁡ ( τ l ) ⁢ R ff ⁡ ( τ l - τ ^ 0 ) ⁢ R ff - 1 ⁡ ( τ k - τ ^ 0 ) ⁢ Λ ss H ⁡ ( τ ^ k ) + ⁢ ( τ ) wherein k is a particular path, Np is the number of visible paths, Rƒƒ(τl–τo) is a double convolution matrix of the filtering process and Rƒƒ−1(τk−–o) is the pseudo inverse, Λss(τl) is the product of spreading and scrambling matrices and ΛssH(τk) is the inverse, and (τ) is noise.

公开(公告)号：US08471597B2

公开(公告)日：2013-06-25

申请号：US12994115

申请日：2009-05-07

申请人： Shenghong Wang ,  Mayan Moudgill ,  Gary Nacer

发明人： Shenghong Wang ,  Mayan Moudgill ,  Gary Nacer

IPC分类号： H03K19/173 ,  H03K19/00 ,  H03K19/096

CPC分类号： G06F1/32 ,  G06F1/04 ,  Y10T29/49117

摘要： A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.

摘要翻译： 描述了包括用于至少一个时钟信号的时钟输入的电路。 只有一个时钟缓冲器被连接到时钟输入端，以便基于至少一个时钟信号产生至少第一修改时钟信号和第二修改时钟信号。 多个触发器连接到时钟缓冲器。 每个触发器接收第一和第二修改的时钟信号。 多个数据输入各自连接到多个触发器中的至少一个，以向多个触发器提供输入数据。 多个数据输出各自连接到多个触发器中的至少一个，以提供来自多个触发器的输出数据。 多个触发器中的每一个利用第一修改时钟信号和第二修改时钟信号将输入数据变换为输出数据。

公开(公告)号：US20110254588A1

公开(公告)日：2011-10-20

申请号：US12994115

申请日：2009-05-07

申请人： Gary Nacer ,  Mayan Moudgill ,  Shenghong Wang

发明人： Gary Nacer ,  Mayan Moudgill ,  Shenghong Wang

IPC分类号： G06F7/38 ,  H01R43/00 ,  H03K3/00

CPC分类号： G06F1/32 ,  G06F1/04 ,  Y10T29/49117

摘要： A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.

摘要翻译： 描述了包括用于至少一个时钟信号的时钟输入的电路。 只有一个时钟缓冲器被连接到时钟输入端，以便基于至少一个时钟信号产生至少第一修改时钟信号和第二修改时钟信号。 多个触发器连接到时钟缓冲器。 每个触发器接收第一和第二修改的时钟信号。 多个数据输入各自连接到多个触发器中的至少一个，以向多个触发器提供输入数据。 多个数据输出各自连接到多个触发器中的至少一个，以提供来自多个触发器的输出数据。 多个触发器中的每一个利用第一修改时钟信号和第二修改时钟信号将输入数据变换为输出数据。

公开(公告)号：US20060294342A1

公开(公告)日：2006-12-28

申请号：US11511677

申请日：2006-08-29

申请人： Mayan Moudgill

发明人： Mayan Moudgill

IPC分类号： G06F15/00

CPC分类号： G06F9/3012 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/3891

摘要： A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue unit.