公开(公告)号：US08959315B2

公开(公告)日：2015-02-17

申请号：US12579867

申请日：2009-10-15

Applicant: Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

Inventor： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

Abstract translation: 多线程处理器包括多个硬件线程单元，耦合到用于解码从其接收的指令的线程单元的指令解码器，以及用于执行解码指令的多个执行单元。 多线程处理器被配置为用于控制与相应硬件线程单元相关联的线程的指令发布序列。 在给定的处理器时钟周期中，仅允许指定的一个线程发出一个或多个指令，但是允许发出指令的指定线程根据指令发布顺序在多个时钟周期内变化。 这些指令以允许至少给定的一个线程支持多个并行指令流水线的方式流水线化。

公开(公告)号：US08892849B2

公开(公告)日：2014-11-18

申请号：US12579893

申请日：2009-10-15

Applicant: Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

Inventor： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC: G06F15/76 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

公开(公告)号：US08819099B2

公开(公告)日：2014-08-26

申请号：US12442374

申请日：2007-09-24

Applicant: Mihai Sima ,  Daniel Iancu ,  Hua Ye ,  Mayan Moudgill

Inventor： Mihai Sima ,  Daniel Iancu ,  Hua Ye ,  Mayan Moudgill

IPC: G06F7/32

CPC classification number: G06F17/16 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3895

Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

Abstract translation: 在无线通信设备中提供数字信号处理器，其中所述处理器包括向量单元，耦合到所述向量单元并由所述向量单元访问的第一和第二寄存器; 以及指令集，其被配置为通过使用向量单元和第一和第二寄存器的坐标旋转数字计算机指令来执行信道值矩阵的矩阵求逆。

公开(公告)号：US08732382B2

公开(公告)日：2014-05-20

申请号：US13057469

申请日：2009-08-05

Applicant: Mayan Moudgill ,  Shenghong Wang

Inventor： Mayan Moudgill ,  Shenghong Wang

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

Abstract translation: 描述了用于DMA引擎的操作的方法。 启动复制以将第一数量的字节从第一源存储器位置传送到第一目的地存储器位置。 然后，在第一个字节数被复制之前发出停止指令。 复制停止后，建立第二个字节数，包含剩下的要复制的字节。 传输停止后，识别出第二个字节数量。 然后生成和存储数量信息。 识别第二源存储器位置以指示第二数量的字节存储在哪里。 然后生成并存储第二源存储器位置信息。 然后识别第二目的地存储器位置以指示要传送第二数量字节的位置。 然后生成并存储第二目的地存储器位置信息。

公开(公告)号：US08171265B2

公开(公告)日：2012-05-01

申请号：US12375202

申请日：2008-12-08

Applicant: Mayan Moudgill ,  Sitij Agrawal

Inventor： Mayan Moudgill ,  Sitij Agrawal

IPC: G06F15/00 ,  G06F9/34

CPC classification number: G06F9/30018 ,  G06F9/345 ,  G06F9/355

Abstract: A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2b bits, using selected b bits of the first index to select at least one target bit in the loaded second value, shifting the target bit into the bottom of the first index, and computing a second index based on the shifting of the target bit into the bottom of the first index. Other methods and variations are also described.

Abstract translation: 描述由处理器上的指令集执行的方法。 该方法包括提供tbbit指令，输入tbbit指令的第一索引，加载用于tbbit指令的第二值，其中使用所选择的第一索引的b位来选择至少一个目标，其中第二值包括至少2b位 将目标位移动到第一索引的底部，并且基于目标位移到第一索引的底部来计算第二索引。 还描述了其它方法和变型。

公开(公告)号：US20110241744A1

公开(公告)日：2011-10-06

申请号：US13061106

申请日：2009-08-20

Applicant: Mayan Moudgill ,  Gary Nacer ,  Shenghong Wang

Inventor： Mayan Moudgill ,  Gary Nacer ,  Shenghong Wang

IPC: H03K3/289

CPC classification number: G06F9/30141 ,  G06F9/30116 ,  G06F9/30123

Abstract: A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.

Abstract translation: 描述用于多线程处理器的处理器寄存器文件。 在一个实施例中，处理器寄存器文件包括具有N个b位宽寄存器的T线程。 每个寄存器包括一个b位主锁存器，连接到主锁存器的T b位从属锁存器和一个从锁存器写使能，连接到从锁存器。 主锁存器不会与从动锁存器同时打开。 此外，在任何给定时间只有一个从锁存器被使能。 对于本领域技术人员来说显而易见的是，T，N和b都是整数。 还提供了其它实施例和变型。

公开(公告)号：US20100241834A1

公开(公告)日：2010-09-23

申请号：US12740423

申请日：2008-08-28

Applicant: Mayan Moudgill

Inventor： Mayan Moudgill

IPC: G06F9/30

CPC classification number: G06F9/30163 ,  G06F9/3016

Abstract: The method selects registers by a register instruction field having x bits. A first group of registers has up to 2y registers and a second group of registers has up to 2z registers where y and z are at least one and not great than x. The method includes encoding an instruction field with x bits wherein y of the x bits designates a register of the first group and z bits of the x bits designates a register of the second group. The register of the first group designated by the y bits of the instruction field and the register of the second group designated by the z bits of the instruction field are selected.

Abstract translation: 该方法通过具有x位的寄存器指令字段来选择寄存器。 第一组寄存器具有最多2个寄存器，第二组寄存器具有高达2z寄存器，其中y和z至少为1，而不是x。 该方法包括用x位编码指令字段，其中x位的y指定第一组的寄存器，x位的z位指定第二组的寄存器。 选择由指令字段的y位指定的第一组的寄存器和由指令字段的z位指定的第二组的寄存器。

公开(公告)号：US20100122068A1

公开(公告)日：2010-05-13

申请号：US12579867

申请日：2009-10-15

Applicant: Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

Inventor： Erdem Hokenek ,  Mayan Moudgill ,  Michael J. Schulte ,  C. John Glossner

IPC: G06F9/30 ,  G06F15/00 ,  G06F9/46 ,  G06F1/04

CPC classification number: G06F9/3851 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3893

Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

公开(公告)号：US07058117B1

公开(公告)日：2006-06-06

申请号：US10530439

申请日：2004-07-26

Applicant: Daniel Iancu ,  John Glossner ,  Mayan Moudgill

Inventor： Daniel Iancu ,  John Glossner ,  Mayan Moudgill

IPC: H04B1/707

CPC classification number: H04B1/7107 ,  H04B1/7115 ,  H04B1/7117 ,  H04B1/712

Abstract: A method of extracting data from a received signal including multi-path interference in a rake receiver. The method includes sampling and filtering the received signal; estimating a time delay τl between paths for the filtered samples ψ(τ); and estimating channel complex coefficient cl for the filtered samples ψ(τ). Transmitted data x(τl) is extracted from the filtered samples ψ(τ) for each path l by solutions of simultaneous equations of the following filtered samples ψ(τ) equation ψ ⁡ ( τ ) ⁢ R ff - 1 ⁡ ( τ k - τ ^ 0 ) ⁢ Λ ss H ⁡ ( τ ^ k ) = ∑ l = 0 N p + 1 ⁢ ⁢ c i ⁡ ( τ l ) × ( τ l ) ⁢ Λ ss ⁡ ( τ l ) ⁢ R ff ⁡ ( τ l - τ ^ 0 ) ⁢ R ff - 1 ⁡ ( τ k - τ ^ 0 ) ⁢ Λ ss H ⁡ ( τ ^ k ) + ⁢ ( τ ) wherein k is a particular path, Np is the number of visible paths, Rƒƒ(τl–τo) is a double convolution matrix of the filtering process and Rƒƒ−1(τk−–o) is the pseudo inverse, Λss(τl) is the product of spreading and scrambling matrices and ΛssH(τk) is the inverse, and (τ) is noise.

公开(公告)号：US06912623B2

公开(公告)日：2005-06-28

申请号：US10161874

申请日：2002-06-04

Applicant: Erdem Hokenek ,  C. John Glossner ,  Arthur Joseph Hoane ,  Mayan Moudgill ,  Shenghong Wang

Inventor： Erdem Hokenek ,  C. John Glossner ,  Arthur Joseph Hoane ,  Mayan Moudgill ,  Shenghong Wang

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0842 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/126 ,  Y02D10/13

Abstract: A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of an address in an access request associated with the cache miss event.

Abstract translation: 用于多线程处理器的高速缓存存储器包括多个设置关联线程高速缓冲存储器，其中一个或多个线程高速缓冲存储器基于访问请求地址来实现逐出过程，所述访问请求地址减少高速缓冲存储器中所需的替换策略存储器的量 。 在说明性实施例中的至少一个线程高速缓存中的给定的一个包括具有多组存储器位置的存储器阵列和用于存储标签的目录，每个对应于存储器位置之一的特定地址的至少一部分。 目录具有多个条目，每个条目存储多个标签，使得如果存储器阵列中存在n组存储器位置，则存在与每个目录条目相关联的n个标签。 该目录用于实现访问请求和存储器阵列的存储器位置之间的集合关联地址映射。 至少部分地基于与高速缓存未命中事件相关联的访问请求中的地址的至少一部分，选择存储器位置中的特定一个存储器位置中的条目以从结合高速缓存未命中事件的给定线程高速缓存中的逐出 。