公开(公告)号：US20230099652A1

公开(公告)日：2023-03-30

申请号：US17991373

申请日：2022-11-21

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20230009674A1

公开(公告)日：2023-01-12

申请号：US17932983

申请日：2022-09-16

Applicant: Apple Inc.

Inventor： Per Hakan Hammarlund ,  Liran Fishel ,  Roman Gindin

IPC: G06F13/16 ,  G06F12/02 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for implementing a memory fetch granule for real-time agents are described. A computing system includes a plurality of real-time agents coupled to memory via an interconnect fabric and a memory controller. The efficiency of the memory controller is determined by the number of bank groups in the memory devices coupled to the memory controller. A memory fetch granule is defined for the memory controller based on the amount of data that can be accessed in parallel on the memory device in back-to-back access cycles. Each real-time agent accumulates memory requests for sequential physical addresses until the amount of data referenced by the requests reaches the size of the memory fetch granule. Once the memory fetch granule is reached, the real-time agent sends the requests to the memory controller via the fabric. This helps to ensure that the requests will arrive at the memory controller near enough to each other to get grouped together.

公开(公告)号：US11475240B2

公开(公告)日：2022-10-18

申请号：US17206901

申请日：2021-03-19

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Assaf Metuki ,  Chuhan Min ,  Wai Yu Trevor Tsang

IPC: G06K9/46 ,  G06K9/62 ,  G06V10/40 ,  G06V10/24 ,  G06V10/75

Abstract: Embodiments relate to generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit and a keypoint descriptor generator circuit. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit determines intensity values of sample points in the pyramid images for a keypoint and determines comparison results of comparisons between the intensity values of pairs of the sample points. The keypoint descriptor generator circuit generate bit values defining the comparison results for the keypoint, each bit value corresponding with one of the comparison results, and generate a sequence of the bit values defining an ordering of the comparison results based on importance levels of the comparisons, where the importance level of each comparison defines how much the comparison is representative of features. Bit values for comparisons having the lowest importance levels may be excluded from the sequence.

公开(公告)号：US20190340491A1

公开(公告)日：2019-11-07

申请号：US15971882

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06N3/08 ,  G06F1/32

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20190340490A1

公开(公告)日：2019-11-07

申请号：US15971872

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Erik K. Norden

IPC: G06N3/04 ,  G06F9/50 ,  G06N3/08

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. The neural processor circuit includes neural engine circuits and a neural task manager circuit. The neural task manager circuit includes multiple task queues and a task arbiter circuit. Each task queue stores a reference to a task list of tasks for a machine learning operation. Each task queue may be associated with a priority parameter. Based on the priority of the task queues, the task arbiter circuit retrieves configuration data for a task from a memory external to the neural processor circuit, and provides the configuration data to components of the neural processor circuit including the neural engine circuits. The configuration data programs the neural processor circuit to execute the task. For example, the configuration data may include input data and kernel data processed by the neural engine circuits to execute the task.