公开(公告)号：US10175982B1

公开(公告)日：2019-01-08

申请号：US15184308

申请日：2016-06-16

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ian D. Kountanis

IPC: G06F9/30 ,  G06F9/38

Abstract: A method and system for storing branch information is disclosed. First data may be stored in a first entry of a first table in response to a determination that a fetched instruction is a branch instruction. Second data that is dependent upon at least one previously taken branch may be stored in a second entry in a second table in response to a determination that a branch associated with the instruction is predicted to be taken. The first data may be updated to include an index to the second data in response to the determination that the branch is predicted to be taken.

公开(公告)号：US20160048395A1

公开(公告)日：2016-02-18

申请号：US14923947

申请日：2015-10-27

Applicant: Apple Inc.

Inventor： Ian D. Kountanis ,  Gerard R. Williams, III ,  James B. Keller

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3844 ,  G06F9/3848

Abstract: In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch.

Abstract translation: 在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。 分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。 在一个实施例中，分支方向预测器可以响应于错误预测而被更新，并且还响应于在预测之间的转换阈值内的分支预测。 为了避免查找以确定是否要执行阈值更新，分支预测器可以在预测期间检测阈值更新，并且可以用分支发送指示。

公开(公告)号：US20150293577A1

公开(公告)日：2015-10-15

申请号：US14251508

申请日：2014-04-11

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Michael L. Karm ,  Ian D. Kountanis ,  David J. Williamson

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

Abstract: Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).

Abstract translation: 公开了在执行指令循环期间降低功率的技术。 处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。 第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。 在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。 在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。

公开(公告)号：US20150227374A1

公开(公告)日：2015-08-13

申请号：US14179204

申请日：2014-02-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ian D. Kountanis

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/381 ,  G06F1/3287 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/30189 ,  G06F9/325 ,  G06F9/3806 ,  G06F9/3844

Abstract: Systems, processors, and methods for determining when to enter loop buffer mode early for loops in an instruction stream. A processor waits until a branch history register has saturated before entering loop buffer mode for a loop if the processor has not yet determined the loop has an unpredictable exit. However, if the loop has an unpredictable exit, then the loop is allowed to enter loop buffer mode early. While in loop buffer mode, the loop is dispatched from a loop buffer, and the front-end of the processor is powered down until the loop terminates.

Abstract translation: 用于确定何时在指令流中循环进入循环缓冲模式的系统，处理器和方法。 如果处理器尚未确定循环具有不可预测的退出，处理器将等待直到分支历史寄存器在进入环路循环缓冲区模式之前饱和。 然而，如果循环有一个不可预测的退出，那么循环允许提前进入循环缓冲模式。 在循环缓冲模式下，循环从循环缓冲区中分派，处理器的前端掉电直到循环终止。

公开(公告)号：US20150205725A1

公开(公告)日：2015-07-23

申请号：US14160242

申请日：2014-01-21

Applicant: APPLE INC.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

Abstract translation: 公开了关于指令模式的缓存的技术。 在一些实施例中，装置包括指令高速缓存，并且被配置为通过指令处理流水线来检测指令的执行模式。 执行模式可能涉及仅在特定指令组中执行指令。 该指令可以包括多次后向控制传送和/或在该模式的一次迭代中采取的控制传送指令，而不是在该模式的另一次迭代中进行。 该设备可以被配置为将指令存储在指令高速缓存中并且从指令高速缓存中取出并执行指令。 该装置可以包括专用于预测指令高速缓存的控制传送指令的方向的分支预测器。 各种实施例可以减少与指令处理相关联的功耗。

公开(公告)号：US20140244976A1

公开(公告)日：2014-08-28

申请号：US13774093

申请日：2013-02-22

Applicant: APPLE INC.

Inventor： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

Abstract: Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

Abstract translation: 用于在IT指令块内处理和预解码分支的各种技术。 指令被取出并缓存在指令高速缓存中，并且生成预解码位以指示IT指令的存在以及IT指令块的可能边界。 如果在IT指令块的可能边界内检测到无条件分支，则无条件分支被视为是条件分支。 无条件分支被发送到分支方向预测器，预测器产生无条件分支的分支方向预测。