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公开(公告)号：US11954048B2
公开(公告)日：2024-04-09
申请号：US17996269
申请日：2021-04-14
Applicant: ARM LIMITED
Inventor： Jason Parker , Yuval Elad , Alexander Donald Charles Chadwick , Andrew Brookfield Swaine , Carlos Garcia-Tobin
CPC classification number: G06F12/1483 , G06F12/1441 , G06F12/145
Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.
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公开(公告)号：US11775177B2
公开(公告)日：2023-10-03
申请号：US17269919
申请日：2019-10-17
Applicant: Arm Limited
Inventor： Yuval Elad , Roberto Avanzi , Jason Parker
IPC: G06F3/06 , G06F16/901 , G06F12/1009
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F12/1009 , G06F16/9027
Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.
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公开(公告)号：US11176061B2
公开(公告)日：2021-11-16
申请号：US16623922
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Gareth Rhys Stockwell , Jason Parker , Matthew Lucien Evans , Martin Weidmann
IPC: G06F12/14
Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). The owner realm has a right to exclude other realms from accessing data within the memory region. Realm management circuitry (20) accesses a realm management tree storing realm management data for at least two realms in a tree structure having a variable number of levels. The realms are identified using a realm identifier which has a variable number of variable length bit portions each providing an index into a given level of the realm management tree.
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公开(公告)号：US11144458B2
公开(公告)日：2021-10-12
申请号：US15549284
申请日：2016-01-12
Applicant: ARM LIMITED
Inventor： Jason Parker , Bruce James Mathewson , Matthew Lucien Evans
IPC: G06F12/00 , G06F12/0831 , G06F12/1009 , G06F12/10
Abstract: An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.
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公开(公告)号：US11086659B2
公开(公告)日：2021-08-10
申请号：US16623569
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Matthew Lucien Evans , Jason Parker , Gareth Rhys Stockwell , Martin Weidmann
Abstract: Processing circuitry (8) processes software processes at one of a plurality of exception levels and in one of a plurality of realms, each realm corresponding to a portion of at least one software process and being associated with a boundary exception level indicating a most privileged exception level at which the realm can be processed by the processing circuitry (8). In response to a realm exiting exception condition during processing of a given realm, where the exception condition is to be handled by an exception handler at a more privileged exception level than the boundary exception level of the given realm, the processing circuitry (8) performs state masking to make inaccessible, to software processes processed at a more privileged exception level than the boundary exception level, architectural state of a subset of registers selected depending on the boundary exception level of the given realm.
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Patent Agency Ranking
36.发明授权公开(公告)号：US11016910B2
公开(公告)日：2021-05-25
申请号：US16623999
申请日：2018-06-11
Applicant: ARM LIMITED
Inventor： Djordje Kovacevic , Jason Parker , Matthew Lucien Evans , Gareth Rhys Stockwell
Abstract: Apparatus for processing data uses memory access circuitry to enforce ownership rights of a plurality of memory regions within a memory, a given memory region among the plurality of memory regions having a given owning process specified from among a plurality of processes. A given owning process has exclusive rights to control access to given owned data stored within the given memory region. The memory access circuitry is responsive to a first access command from a first processing element for the given memory region to perform an access sequence comprising switching a lock flag for the given memory region to a locked state, performing an access operation specified by the access command, and switching the lock flag to an unlocked state. The memory access circuitry is responsive to a second access command from a second processing element for the given memory region while the lock flag is in said locked state to block action of the second access command.
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公开(公告)号：US10762226B2
公开(公告)日：2020-09-01
申请号：US16071915
申请日：2017-02-10
Applicant: ARM Limited
Inventor： Jason Parker
Abstract: A data processing system 2 operates at a plurality of exception levels ELx and supports the use of protected execution environments. A register bank 16 contains registers having associated ownership variables indicating an owning exception level. Register access control circuitry 30 is responsive to the ownership values for respective registers to control access to those registers by processing circuitry 14 in dependence upon the ownership values. Target-constrained data transfer operations and associated program instructions may be provided which are able to access data values in registers not owned by the exception level associated with the execution of those program instructions, but are limited to perform data transfers to or from memory locations within a memory 6 indicated by an architected storage pointer for the owning exception level. Target-unconstrained transfer instructions at a given exception level are not able to access register data value marked as owned by a different exception level.
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公开(公告)号：US10649787B2
公开(公告)日：2020-05-12
申请号：US15759907
申请日：2016-09-09
Applicant: ARM LIMITED
Inventor： Jason Parker , Richard Roy Grisenthwaite
Abstract: A data processing system includes exception handling circuitry to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank. Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.
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公开(公告)号：US09619387B2
公开(公告)日：2017-04-11
申请号：US14186091
申请日：2014-02-21
Applicant: ARM LIMITED
Inventor： Matthew L. Evans , Hakan Lars-Goran Persson , Jason Parker , Gareth Stockwell , Andrew Christopher Rose
IPC: G06F12/08 , G06F12/10 , G06F9/30 , G06F12/0831 , G06F12/1009 , G06F12/109 , G06F12/1027
CPC classification number: G06F12/0833 , G06F9/3004 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/109 , G06F2212/1016 , G06F2212/65 , G06F2212/683
Abstract: A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.
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公开(公告)号：US20150293775A1
公开(公告)日：2015-10-15
申请号：US14682310
申请日：2015-04-09
Applicant: ARM Limited
Inventor： Hakan Persson , Matt Evans , Jason Parker , Marc Zyngier
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F2009/45579 , G06F2009/45583
Abstract: A data processing system comprises one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. The system also comprises an accelerator that provides a shared resource for a plurality of the applications, an input/output module comprising one or more input/output interfaces for the submission of tasks to the accelerator, a hypervisor that manages the allocation of the input/output interfaces to the one or more operating systems and a storage area accessible by the hypervisor and the accelerator. The accelerator is capable of writing one or more selected pieces of information representative of one or more scheduling statistics of the accelerator periodically to the storage area without having received a request for the one or more selected pieces of information from the hypervisor.
Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行一个或多个操作系统。 每个操作系统包括一个或多个应用程序。 该系统还包括为多个应用提供共享资源的加速器，包括用于向加速器提交任务的一个或多个输入/输出接口的输入/输出模块，管理程序，用于管理输入/ 输出到一个或多个操作系统的接口以及由管理程序和加速器可访问的存储区域。 加速器能够将表示加速器的一个或多个调度统计信息的一个或多个选定的信息段周期性地写入存储区域，而不从管理程序接收到对于一个或多个所选择的信息的请求。
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