公开(公告)号：US10048720B2

公开(公告)日：2018-08-14

申请号：US15831732

申请日：2017-12-05

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09864399B2

公开(公告)日：2018-01-09

申请号：US14965073

申请日：2015-12-10

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09747435B2

公开(公告)日：2017-08-29

申请号：US14696581

申请日：2015-04-27

Applicant: Apple Inc.

Inventor： Timothy R. Paaske ,  Weihua Mao ,  Shu-Yi Yu

IPC: G06F21/00 ,  G06F21/46 ,  G06F21/60

CPC classification number: G06F21/46 ,  G06F21/44 ,  G06F21/602 ,  G06F21/606 ,  G06F21/85 ,  G06F2221/2137 ,  H04L9/088

Abstract: An apparatus, a method, and a system are presented in which the apparatus may include a security circuit, a processor, and an interface controller. The security circuit may be configured to generate a keyword. The processor may be configured to determine one or more policies to be applied to usage of the keyword, and to generate a policy value. The policy value may include one or more data bits indicative of the determined one or more policies. The interface controller may be configured to generate a message including the keyword and the policy value. The interface controller may also be configured to send the message.

公开(公告)号：US09647653B2

公开(公告)日：2017-05-09

申请号：US14730473

申请日：2015-06-04

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Jean-Didier Allegrucci ,  Timothy Paaske ,  Deniz Balkan

IPC: H03K5/19 ,  H03K5/26

CPC classification number: H03K5/19 ,  H03K5/26

Abstract: An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

公开(公告)号：US20160124771A1

公开(公告)日：2016-05-05

申请号：US14532630

申请日：2014-11-04

Applicant: Apple Inc.

Inventor： Shu-Yi Yu

IPC: G06F9/48 ,  G06F13/24

CPC classification number: G06F9/4825 ,  G06F13/24

Abstract: Techniques are disclosed relating to processor power control and interrupts. In one embodiment, an apparatus includes a processor configured to assert an indicator that the processor is suspending execution of instructions until the processor receives an interrupt. In this embodiment, the apparatus includes power circuitry configured to alter the power provided to the processor based on the indicator. In this embodiment, the apparatus includes throttling circuitry configured to, in response to receiving a request from the power circuitry to alter the power provided to the processor, block the request until the end of a particular time interval subsequent to receipt of the request or de-assertion of the indicator. In some embodiments, the particular time interval corresponds to latency between the processor receiving an interrupt and de-asserting the indicator.

Abstract translation: 公开了涉及处理器功率控制和中断的技术。 在一个实施例中，一种装置包括处理器，其被配置为断言指示符，该处理器暂停执行指令，直到处理器接收到中断。 在该实施例中，该装置包括被配置为基于指示符改变提供给处理器的功率的电源电路。 在该实施例中，该装置包括节流电路，其被配置为响应于从电力电路接收到改变提供给处理器的功率的请求，阻止该请求，直到在接收请求或de之后的特定时间间隔结束 - 指示符的使用。 在一些实施例中，特定时间间隔对应于处理器接收中断和取消断言指示符之间的等待时间。

公开(公告)号：US09262362B2

公开(公告)日：2016-02-16

申请号：US14041818

申请日：2013-09-30

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Timothy R. Paaske

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/40 ,  G06F9/38

CPC classification number: G06F13/4068 ,  G06F9/3869 ,  G06F13/4217 ,  G06F2213/0038

Abstract: A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.

Abstract translation: 公开了可以补偿可能随总线的操作条件而变化的总线时序的系统。 该系统可以包括通信总线，被配置为经由通信总线发送数据的第一功能单元和被配置为经由总线接收数据的第二功能单元。 第一功能单元可以经由通信总线向第二功能单元发送第一值。 第一功能单元还可以被配置为响应于从发送第一数据值开始经过第一时间段的确定来断言数据有效信号。 第二功能单元可以被配置为接收第一数据值并且取决于数据有效信号对第一数据值进行采样。

公开(公告)号：US20150095535A1

公开(公告)日：2015-04-02

申请号：US14041818

申请日：2013-09-30

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Timothy R. Paaske

IPC: G06F13/40

CPC classification number: G06F13/4068 ,  G06F9/3869 ,  G06F13/4217 ,  G06F2213/0038

Abstract: A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.

Abstract translation: 公开了可以补偿可能随总线的操作条件而变化的总线时序的系统。 该系统可以包括通信总线，被配置为经由通信总线发送数据的第一功能单元和被配置为经由总线接收数据的第二功能单元。 第一功能单元可以经由通信总线向第二功能单元发送第一值。 第一功能单元还可以被配置为响应于从发送第一数据值开始经过第一时间段的确定来断言数据有效信号。 第二功能单元可以被配置为接收第一数据值并且取决于数据有效信号对第一数据值进行采样。

公开(公告)号：US20140089682A1

公开(公告)日：2014-03-27

申请号：US13626566

申请日：2012-09-25

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Michael J. Smith ,  Shu-Yi Yu

IPC: G06F21/00

CPC classification number: G06F21/72 ,  G06F21/575

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。