公开(公告)号：US20130246820A1

公开(公告)日：2013-09-19

申请号：US13889840

申请日：2013-05-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander J. Branover ,  Ashish Jain ,  Ann M. Ling ,  Maurice B. Steinman

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.

Abstract translation: 公开了用于动态调整处理节点和其他组件（诸如外围接口）的组件的功率限制的装置和方法。 该设备包括多个处理节点和其他组件，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置对于至少一个处理节点的第一频率限制。 对于没有可靠的功耗报告或成本或省电原因的组件，初始功率限制设置在保护带功率限制以下。 处理节点的节流量用于调整处理节点和这些组件的功率限制。

公开(公告)号：US20240211014A1

公开(公告)日：2024-06-27

申请号：US18146733

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Tzyy-Juin Kao ,  Ashish Jain ,  Rashad Oreifej

IPC: G06F1/324 ,  G06F1/3218

CPC classification number: G06F1/324 ,  G06F1/3218

Abstract: Systems, apparatuses, and methods for implementing efficient power optimization in a computing system are disclosed. A system management unit records operating frequencies required for a computing component to execute a first task. The system management unit stores the recorded operating frequencies in a data array or any other predetermined memory location of a computing system. The system management unit uses the recorded operating frequencies to determine operating frequencies for execution of one or more other tasks.

公开(公告)号：US20220189576A1

公开(公告)日：2022-06-16

申请号：US17121110

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

IPC: G11C29/50 ,  H03K3/03 ,  G11C7/22

Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

公开(公告)号：US20160266628A1

公开(公告)日：2016-09-15

申请号：US14641510

申请日：2015-03-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Benjamin David Bates ,  Ali Akbar Merrikh ,  Samuel David Naffziger ,  Steven Frederick Liepe ,  Madhu Saravana Sibi Govindan

IPC: G06F1/28 ,  G01K13/00

CPC classification number: G06F1/28 ,  G01K1/143 ,  G01K7/42 ,  G01K13/00 ,  G06F1/206 ,  G06F1/3206

Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.

Abstract translation: 一种方法包括基于容纳计算系统的设备的外表面上的至少一个位置的确定的皮肤温度来控制计算系统的功率限制。 处理器包括处理单元和功率管理控制器，用于基于容纳处理器的设备的外表面上的至少一个位置的确定的皮肤温度来控制处理单元的功率限制。

公开(公告)号：US09261949B2

公开(公告)日：2016-02-16

申请号：US13889840

申请日：2013-05-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Ashish Jain ,  Ann M. Ling ,  Maurice B. Steinman

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.

Abstract translation: 公开了用于动态调整处理节点和其他组件（诸如外围接口）的组件的功率限制的装置和方法。 该设备包括多个处理节点和其他组件，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置对于至少一个处理节点的第一频率限制。 对于没有可靠的功耗报告或成本或省电原因的组件，初始功率限制设置在保护带功率限制以下。 处理节点的节流量用于调整处理节点和这些组件的功率限制。

公开(公告)号：US20150277521A1

公开(公告)日：2015-10-01

申请号：US14225244

申请日：2014-03-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ashish Jain ,  Alexander J. Branover ,  Guhan Krishnan

IPC: G06F1/26

CPC classification number: G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.

Abstract translation: 系统具有包括存储器，耦合到存储器的PHY和一个或多个其它电子部件的多个电子部件。 在系统运行期间估计PHY消耗的功率。 估计PHY消耗的功率包括将PHY消耗的功率建模为相对于存储器带宽的线性函数。 至少部分地基于PHY消耗的估计功率来确定PHY的可用功率。 用于PHY的可用功率的至少一部分被分配给一个或多个其它组件中的至少一个。

公开(公告)号：US20150073611A1

公开(公告)日：2015-03-12

申请号：US14021279

申请日：2013-09-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Alexander J. Branover

IPC: G05B13/02 ,  G01R31/02

CPC classification number: G01R31/025 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: An operating point of one or more components in a processing device may be set using a leakage current estimated based on at least one of a rate of temperature overages or a rate of power overages. In some embodiments, a power management controller may be used to set an operating point of one or more components in the processing device based on at least one of a rate of temperature overages or a rate of power overages for the component(s).

Abstract translation: 处理装置中的一个或多个部件的操作点可以使用基于温度超标率或功率超载率中的至少一个估计的泄漏电流来设置。 在一些实施例中，功率管理控制器可以用于基于温度过高的速率或组件的功率过载速率中的至少一个来设置处理设备中的一个或多个组件的工作点。

公开(公告)号：US20250111121A1

公开(公告)日：2025-04-03

申请号：US18478469

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Lakshminarayana Pappu

IPC: G06F30/373

Abstract: An apparatus and method for efficiently managing performance and power consumption among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. An integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with a corresponding communication fabric for routing packets. A second functional block placed between a first functional block and a third functional block routes packets to destinations from at least the first and the third functional blocks, and provides higher performance than the first and the third functional blocks due to semiconductor manufacturing variations. A power manager assigns a single power supply voltage to the replicated functional blocks, and assigns a target clock frequency to the first and the third functional blocks. The power manager assigns another clock frequency greater than the target clock frequency to the second functional block.

公开(公告)号：US20160378168A1

公开(公告)日：2016-12-29

申请号：US14751515

申请日：2015-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Ashish Jain ,  Sridhar V. Gada

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: Systems, apparatuses, and methods for managing power usage of integrated circuits. One or more processor cores may be powered down when the system is idle. Even if there is no user activity, the processor core(s) may be woken up periodically for background downloads to retrieve the latest status for social media and other applications. Additionally, a power management unit may track the average number of active cores and the average core utilization. If the average number of active cores is less than a first threshold and the average core utilization is less than a second threshold, the power management unit may generate a request to offline one or more cores. Still further, when the processor's skin temperature is above a threshold and all of the cores are operating at the lowest acceptable operating point, one or more cores may be powered down.

Abstract translation: 用于管理集成电路的电力使用的系统，设备和方法。 当系统空闲时，一个或多个处理器内核可能会关闭电源。 即使没有用户活动，也可以周期性地唤醒处理器核心以进行背景下载以检索社交媒体和其他应用程序的最新状态。 此外，电源管理单元可以跟踪活动核心的平均数量和平均核心利用率。 如果活动核心的平均数量小于第一阈值，并且平均核心利用率小于第二阈值，则电源管理单元可以产生离线一个或多个核心的请求。 此外，当处理器的皮肤温度高于阈值并且所有核心都在最低可接受的工作点运行时，一个或多个核心可以掉电。

公开(公告)号：US11462294B2

公开(公告)日：2022-10-04

申请号：US17121110

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

IPC: G11C7/10 ,  G11C29/50 ,  G11C7/22 ,  H03K3/03

Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.