公开(公告)号：US07535957B2

公开(公告)日：2009-05-19

申请号：US11104586

申请日：2005-04-13

申请人： Seiichi Ozawa ,  Jun-ichi Okamura ,  Yohei Ishizone ,  Satoshi Miura

发明人： Seiichi Ozawa ,  Jun-ichi Okamura ,  Yohei Ishizone ,  Satoshi Miura

IPC分类号： H03K7/08

CPC分类号： H04L7/033 ,  H03K7/10 ,  H03L7/087 ,  H03L7/091 ,  H03L7/113 ,  H04L25/45 ,  H04L25/4902

摘要： [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation.[Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

摘要翻译： [问题]实现不需要参考时钟和握手操作的数字数据的可靠而稳定的传输。 解决问题的手段本发明提供一种用于在第一周期和第二周期中分别交替地和周期性地传送第一信息和第二信息的数字数据传送方法，其中：每单位时间的第一信息的信息量 在第一期间中，比第二期间的每单位时间的第二信息的信息量大; 并且第一周期中的第二信息作为脉冲宽度调制的串行数据传送。

公开(公告)号：US20080246511A1

公开(公告)日：2008-10-09

申请号：US10585914

申请日：2005-04-28

申请人： Satoshi Miura ,  Jun-ichi Okamura ,  Seiichi Ozawa

发明人： Satoshi Miura ,  Jun-ichi Okamura ,  Seiichi Ozawa

IPC分类号： H03K19/0175 ,  H03K3/00

CPC分类号： H03F3/45179 ,  H03F3/45183 ,  H03F3/505 ,  H03F2203/45318 ,  H03F2203/45466 ,  H04L25/0272 ,  H04L25/028

摘要： A differential driving circuit used for low voltage differential signals and an electronic device incorporating the same are provided wherein no differential amplifiers are used or the number of differential amplifiers are reduced, thereby reducing the circuit area and the current consumption and further solving the problem of oscillation caused by noise, while a high driving performance is achieved. There are included a switch circuit an output circuit and a reference potential generating circuit. The switch circuit, which comprises MOS transistors, receives differential signals and outputs current signals. The output circuit comprises an NMOS transistor, an end of which is connected to the power supply potential of a higher potential side, the other end of which is connected to a node of the switch circuit and which acts as a source follower, and an PMOS transistor, an end of which is connected to the power supply potential of a lower potential side, the other end of which is connected to the other node of the switch circuit and which acts as a source follower. The reference potential generating circuit supplies reference potentials to the respective gates of the PMOS and NMOS transistors. The reference potential generating circuit includes a potential varying means that varies the differential potentials with an offset potential kept constant. Further, there is included an emphasis circuit for the output circuit.

摘要翻译： 提供了用于低电压差分信号的差分驱动电路和包括其的电子器件，其中不使用差分放大器或减少差分放大器的数量，从而减少电路面积和电流消耗，并进一步解决振荡问题 由噪音引起，同时实现了较高的驾驶性能。 包括开关电路，输出电路和参考电位产生电路。 包含MOS晶体管的开关电路接收差分信号并输出​​电流信号。 输出电路包括NMOS晶体管，其一端连接到较高电位侧的电源电位，另一端连接到开关电路的一个节点并用作源极跟随器，PMOS 晶体管，其端部连接到较低电位侧的电源电位，另一端连接到开关电路的另一个节点，用作源极跟随器。 参考电位产生电路将参考电位提供给PMOS和NMOS晶体管的各个栅极。 参考电位产生电路包括电位改变装置，其以保持不变的偏移电位来改变差分电位。 此外，还包括用于输出电路的加重电路。

公开(公告)号：US07391716B2

公开(公告)日：2008-06-24

申请号：US10477713

申请日：2002-05-28

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H04J7/00

CPC分类号： H04N1/00119 ,  H04L7/0008 ,  H04L25/4902 ,  H04N1/00095 ,  H04N1/36 ,  H04N7/06

摘要： A semiconductor integrated circuit which transmits voice data as ancillary data while maintaining transmission quality without increasing the number of transmission cables in a system for carrying out serial transmission of image data as main data. The semiconductor integrated circuit includes a main data transmitting circuit for converting main data into serial data and transmitting the serial data via at least one transmission path in synchronization with a clock signal, and an ancillary data transmitting circuit for pulse-width-modulating the clock signal by using ancillary data to generate a modulated clock signal having at least three kinds of pulse widths in a predetermined order and transmitting the modulated clock signal via another transmission path.

摘要翻译： 一种半导体集成电路，其将语音数据作为辅助数据发送，同时保持传输质量，而不增加用于执行图像数据的串行传输的系统中的传输电缆的数量作为主数据。 半导体集成电路包括主数据发送电路，用于将主数据转换为串行数据，并通过与时钟信号同步的至少一个传输路径发送串行数据;以及辅助数据发送电路，用于对时钟信号进行脉冲宽度调制 通过使用辅助数据以预定顺序产生具有至少三种脉冲宽度的调制时钟信号，并经由另一传输路径发送调制时钟信号。

公开(公告)号：US06667663B2

公开(公告)日：2003-12-23

申请号：US10197650

申请日：2002-07-16

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H03L700

CPC分类号： H03L7/0805 ,  H03L7/07 ,  H03L7/08 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/095

摘要： A PLL circuit having a gain control function includes: a first phase comparator for outputting a first phase difference signal indicating a phase difference between a first input signal and a second input signal; a first loop filter for smoothing a signal based on the first phase difference signal and outputting a first control voltage; a VCO for oscillating at a frequency based on the first control voltage and thereby outputting a first clock; and a dummy VCO having characteristics identical with those of the VCO for oscillating at a frequency based on a second control voltage and thereby outputting a second clock.

摘要翻译： 具有增益控制功能的PLL电路包括：第一相位比较器，用于输出指示第一输入信号和第二输入信号之间的相位差的第一相位差信号; 第一环路滤波器，用于基于所述第一相位差信号平滑信号并输出​​第一控制电压; VCO，用于基于第一控制电压以频率振荡，从而输出第一时钟; 以及具有与VCO相同特性的虚拟VCO，用于以基于第二控制电压的频率振荡，从而输出第二时钟。

公开(公告)号：US4594513A

公开(公告)日：1986-06-10

申请号：US473132

申请日：1983-03-07

申请人： Osamu Suzuki ,  Kanjiro Ishizaki ,  Seiichi Ozawa

发明人： Osamu Suzuki ,  Kanjiro Ishizaki ,  Seiichi Ozawa

IPC分类号： C04B41/61 ,  B28B7/28 ,  B65D90/02 ,  C25D15/02 ,  G21F5/00 ,  G21F5/005 ,  G21F9/00 ,  G21F9/36

CPC分类号： G21F5/005

摘要： A multiplex design container, is herein disclosed, that comprises a metallic vessel as an outer layer, a concrete lining as an inner layer that is formed on the inner surface of the metallic vessel and which is reinforced with a reinforcing material and strengthened with an impregnant, and a polymerized and cured impregnant layer as an intermediate layer that is formed between said metallic vessel and the concrete lining.

摘要翻译： 本文公开了一种复合设计容器，其包括作为外层的金属容器，作为内层的混凝土衬里，其形成在金属容器的内表面上并且用增强材料增强并用浸渍剂增强 以及形成在所述金属容器和混凝土衬里之间的作为中间层的聚合和固化的浸渍剂层。