公开(公告)号：US07283005B2

公开(公告)日：2007-10-16

申请号：US11055539

申请日：2005-02-09

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

IPC: H03K3/03

CPC classification number: H03H11/26 ,  H03K5/04 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00123 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03K2005/00195

Abstract: The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.

Abstract translation: 电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路， 连接到第一和第二振荡器的公共输出端的输出端子。 第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。

公开(公告)号：US20050258998A1

公开(公告)日：2005-11-24

申请号：US11113954

申请日：2005-04-25

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno

IPC: G11C27/02 ,  H03H19/00 ,  H03K5/24 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

CPC classification number: G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

Abstract: A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated/deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

Abstract translation: 一种开关电容电路，包括：开关电容部分，其能够接收信号并执行所述信号的采样，所述部分包括至少一组电容器，每个电容器的一组电容器具有连接到公共节点的端子; 至少包括连接到所述公共节点的输入端的操作级，所述操作级在所述信号的采样时间间隔期间向所述公共节点提供电流，以对所述电容器组进行充电。 该电路还包括连接到所述公共节点的辅助电路，并且能够通过用于将另外的电流注入到所述公共节点中的使能信号来激活/去激活，并且在至少等于一个等待时间间隔的至少一个时间间隔期间增加提供给所述公共节点的电流 所述采样间隔的分数。

公开(公告)号：US06720903B2

公开(公告)日：2004-04-13

申请号：US10172376

申请日：2002-06-14

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC: H03M112

CPC classification number: H03M1/181 ,  H03M1/468

Abstract: A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.

Abstract translation: 一种操作SAR型模数转换器以匹配要转换的输入电压信号的动态范围与转换器的满量程范围的方法，所述转换器包括至少一个二进制加权电容器阵列。 该方法包括获得数字增益代码的步骤，该数字增益代码表示满量程范围和要转换的电压信号的动态范围之间的比率，将要转换的电压信号施加到电容器阵列，以便对电压进行充电 信号仅转换具有与具有选定二进制值的增益码的位相同的二进制权重的阵列电容器，并且根据SAR选择性地将阵列的电容器耦合到第一和第二预定参考电压端子之一 技术，以获得对应于输入电压信号的输出数字代码。

公开(公告)号：US06600437B1

公开(公告)日：2003-07-29

申请号：US10115272

申请日：2002-04-01

Applicant: Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

Inventor： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

IPC: H03M166

CPC classification number: H03M1/68 ,  H03M1/468 ,  H03M1/804

Abstract: A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

Abstract translation: 开关电容器数模转换器包括具有相应的第二和第二二进制加权电容器阵列的第一和第二转换器段。 第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。 第二段的每个电容器具有连接到第二公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。 该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。 耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2p-1）.C-CATT = 2p.C，其中p是在第一转换器段中编码的位数，C是 单位电容。