公开(公告)号：US20060009886A1

公开(公告)日：2006-01-12

申请号：US11227075

申请日：2005-09-16

Applicant: Kohei Sakurai ,  Nobuyasu Kanekawa ,  Fumio Murabayashi ,  Mitsuru Watabe ,  Toshio Hayashibara

Inventor： Kohei Sakurai ,  Nobuyasu Kanekawa ,  Fumio Murabayashi ,  Mitsuru Watabe ,  Toshio Hayashibara

IPC: G06F19/00

CPC classification number: B60W50/00 ,  B60T8/885 ,  B60T2270/406 ,  B60W50/0205 ,  B60W2050/0006 ,  F02D41/22 ,  F02D41/266 ,  F02D41/3005 ,  F02D2400/18

Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

公开(公告)号：US06657459B2

公开(公告)日：2003-12-02

申请号：US10143762

申请日：2002-05-14

Applicant: Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

Inventor： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

IPC: H03K19096

CPC classification number: H03K3/3565 ,  H03K19/018521

Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

公开(公告)号：US06377480B1

公开(公告)日：2002-04-23

申请号：US09928442

申请日：2001-08-14

Applicant: Takashi Sase ,  Fumio Murabayashi ,  Mutsumi Kikuchi

Inventor： Takashi Sase ,  Fumio Murabayashi ,  Mutsumi Kikuchi

IPC: H02M112

CPC classification number: H02M1/36 ,  Y10S323/901

Abstract: In a switching power source comprising a triangular wave generating circuit and an error amplifier and a PWM comparator, in normal time PWM pulses being obtained by comparing an output amplitude of triangular wave of the triangular wave generating circuit with an output voltage of the error amplifier as a reference voltage using the PWM comparator, the soft-start circuit of the switching power source comprises a soft-start reference value setting part composed of a group of resistance networks and a group of switches using the same structure as an upper-and-lower limit setting part, composed of networks and switches, for setting an upper and a lower limits of the amplitude of triangular wave of the triangular generating circuit; and a counting circuit for counting cycles of the triangular wave of the triangular wave generating circuit to obtain a plurality of arbitrary soft-start timings in order to switch the group of switches.

Abstract translation: 在包括三角波发生电路和误差放大器和PWM比较器的开关电源中，在正常时间PWM脉冲是通过将三角波产生电路的三角波的输出振幅与误差放大器的输出电压进行比较而获得的， 使用PWM比较器的参考电压，开关电源的软启动电路包括由一组电阻网络组成的软启动基准值设定部分和使用与上下相同结构的一组开关 限制设定部分，由网络和开关组成，用于设定三角形发生电路三角波振幅的上限和下限; 以及计数电路，用于对三角波产生电路的三角波的周期进行计数，以获得多个任意的软启动定时，以切换开关组。

公开(公告)号：US5931895A

公开(公告)日：1999-08-03

申请号：US789430

申请日：1997-01-29

Applicant: Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

Inventor： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

IPC: G06F7/38 ,  G06F5/01 ,  G06F7/00 ,  G06F7/483 ,  G06F7/74 ,  G06F7/76 ,  G06F7/52

CPC classification number: G06F5/012 ,  G06F7/483

Abstract: A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

Abstract translation: 一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路 移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。 浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在 在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。 在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

公开(公告)号：US5869990A

公开(公告)日：1999-02-09

申请号：US792799

申请日：1997-02-03

Applicant: Fumio Murabayashi ,  Tatsumi Yamauchi ,  Yutaka Kobayashi

Inventor： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Yutaka Kobayashi

IPC: G06F7/00 ,  G06F9/38 ,  G06F15/78 ,  H04L7/00 ,  H03K5/13

CPC classification number: G06F9/3869

Abstract: A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.

Abstract translation: 提供一种半导体集成电路器件，其包括至少一个第一功能电路块，其接收输入信号并执行逻辑运算以输出输出信号。 至少一个第二功能电路块与第一功能电路块并联连接。 第二功能电路块还响应输入信号以执行逻辑运算并输出输出信号作为结果。 第一和第二功能电路块彼此连接，使得第二功能电路块将与第一功能电路块同步操作。 更具体地，第一功能电路块被布置成控制第二功能电路块的输出定时。

公开(公告)号：US5377136A

公开(公告)日：1994-12-27

申请号：US076874

申请日：1993-06-15

Applicant: Yoji Nishio ,  Fumio Murabayashi ,  Shoichi Kotoku ,  Akira Uragami ,  Manabu Shibata ,  Yoshitatsu Kojima ,  Fumiaki Matsuzaki

Inventor： Yoji Nishio ,  Fumio Murabayashi ,  Shoichi Kotoku ,  Akira Uragami ,  Manabu Shibata ,  Yoshitatsu Kojima ,  Fumiaki Matsuzaki

IPC: G11C5/06 ,  G11C8/16

CPC classification number: G11C8/16 ,  G11C5/063

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract translation: 公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。 因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

公开(公告)号：US20050237039A1

公开(公告)日：2005-10-27

申请号：US10524087

申请日：2003-08-08

Applicant: Mutsumi Kikuchi ,  Noboru Akiyama ,  Hiroyuki Shoji ,  Fumio Murabayashi ,  Akihiko Kanouda ,  Takashi Sase ,  Koji Tateno

Inventor： Mutsumi Kikuchi ,  Noboru Akiyama ,  Hiroyuki Shoji ,  Fumio Murabayashi ,  Akihiko Kanouda ,  Takashi Sase ,  Koji Tateno

IPC: G05F1/40 ,  G11C5/14 ,  H01L27/06 ,  H01L27/08 ,  H02M3/156

CPC classification number: G11C5/147 ,  H01L27/0688 ,  H01L27/08 ,  H02M3/156 ,  H02M2001/007

Abstract: A semiconductor device capable of achieving downsizing without reducing the power supply efficiency and capable of reducing switching noises and a memory card using the same are disclosed. The device comprises a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit for controlling an output voltage at a nearby location of the final stage, and one or more internal elements to which the final output voltage is supplied. A primary voltage booster circuit at the first stage includes an inductance element, a switching element, a diode and a driver circuit. At a metal core part of the inductance element, a metal wiring line is used, which was formed by use of a fabrication process of semiconductor integrated circuits, while employing for its core part an inter-wiring layer dielectric film that was formed using the fabrication process. In addition, the switching element and the diode are arranged so that portions thereof are disposed beneath the inductance element.

Abstract translation: 公开了能够实现小型化而不降低电源效率并且能够降低开关噪声的半导体器件和使用其的存储卡。 该装置包括用于潜在地提高最终输出电压的电源电压的多级升压电路，用于控制最后级的附近位置处的输出电压的电压控制单元和一个或多个内部元件 其提供最终输出电压。 第一级的初级升压电路包括电感元件，开关元件，二极管和驱动器电路。 在电感元件的金属芯部分，使用通过使用半导体集成电路的制造工艺形成的金属布线，同时使用其核心部分使用该制造形成的布线层电介质膜 处理。 此外，开关元件和二极管被布置成使得其部分设置在电感元件下方。

公开(公告)号：US06798255B2

公开(公告)日：2004-09-28

申请号：US09931250

申请日：2001-08-17

Applicant: Fumikazu Takahashi ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Kazuhisa Miyamoto ,  Kazuharu Kuchimachi

Inventor： Fumikazu Takahashi ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Kazuhisa Miyamoto ,  Kazuharu Kuchimachi

IPC: H03B2100

CPC classification number: H03K5/15013

Abstract: A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.

Abstract translation: 一种半导体集成电路装置，包括驱动电路，连接到驱动电路的第一长距离布线和连接在第一长距离布线的整个长度上的多个门电路，使得驱动电路的输出信号 经由第一长距离布线由多个门电路接收，其中布置在连接到驱动电路的输入端的门电路的输入端附近的节点和第一长距离布线的端部 通过第二长距离布线和增速电路连接。

公开(公告)号：US06625522B2

公开(公告)日：2003-09-23

申请号：US09801656

申请日：2001-03-09

Applicant: Kohei Sakurai ,  Nobuyasu Kanekawa ,  Fumio Murabayashi ,  Mitsuru Watabe ,  Toshio Hayashibara

Inventor： Kohei Sakurai ,  Nobuyasu Kanekawa ,  Fumio Murabayashi ,  Mitsuru Watabe ,  Toshio Hayashibara

IPC: G06F700

CPC classification number: B60W50/00 ,  B60T8/885 ,  B60T2270/406 ,  B60W50/0205 ,  B60W2050/0006 ,  F02D41/22 ,  F02D41/266 ,  F02D41/3005 ,  F02D2400/18

Abstract: A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

Abstract translation: 低成本车辆控制系统和使用该系统的汽车控制致动器驱动器的辐射，从而降低辐射部件成本，并允许电子控制单元的小型化以提高通用性。 车辆控制系统具有电子控制单元，用于在致动器侧驱动致动器的多个致动器和致动器驱动器。 执行器驱动器分别具有独立的自诊断部分，自保护部分和通信控制部分，并且相应地分散到致动器。

公开(公告)号：US06590425B2

公开(公告)日：2003-07-08

申请号：US09887065

申请日：2001-06-25

Applicant: Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

Inventor： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

IPC: H03K19096

CPC classification number: H03K19/00338

Abstract: There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented. There is also disclosed a parallel data processing apparatus which features such logic circuitry, the data processing apparatus having both a plurality of data processing units, each having a processor and a memory, and a plurality of hard disks.

Abstract translation: 公开了一种电路装置，其高度耐受噪声并以比传统的完全互补的静态CMOS电路更高的速度工作。 为了实现这一点，电路装置具有串联连接的多个CMOS静态逻辑电路和连接到这些逻辑电路的输出部分的电位设置电路，并将输出部分的输出与 时钟信号，从而通过NMOS电路的操作传播信号。 换句话说，信号传播延迟仅在N型逻辑块导通时才发生。 因此，可以防止电路操作加剧，并且可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。 还公开了一种具有这种逻辑电路的并行数据处理装置，数据处理装置具有多个数据处理单元，每个数据处理单元具有处理器和存储器，以及多个硬盘。