公开(公告)号：US5265045A

公开(公告)日：1993-11-23

申请号：US793315

申请日：1991-11-15

Applicant: Yoji Nishio ,  Fumio Murabayashi ,  Shoichi Kotoku ,  Akira Uragami ,  Manabu Shibata ,  Yoshitatsu Kojima ,  Fumiaki Matsuzaki

Inventor： Yoji Nishio ,  Fumio Murabayashi ,  Shoichi Kotoku ,  Akira Uragami ,  Manabu Shibata ,  Yoshitatsu Kojima ,  Fumiaki Matsuzaki

IPC: G11C5/06 ,  G11C8/16 ,  G11C7/00 ,  G11C5/00 ,  G11C8/00

CPC classification number: G11C8/16 ,  G11C5/063

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract translation: 公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。 因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

公开(公告)号：US5377136A

公开(公告)日：1994-12-27

申请号：US076874

申请日：1993-06-15

Applicant: Yoji Nishio ,  Fumio Murabayashi ,  Shoichi Kotoku ,  Akira Uragami ,  Manabu Shibata ,  Yoshitatsu Kojima ,  Fumiaki Matsuzaki

Inventor： Yoji Nishio ,  Fumio Murabayashi ,  Shoichi Kotoku ,  Akira Uragami ,  Manabu Shibata ,  Yoshitatsu Kojima ,  Fumiaki Matsuzaki

IPC: G11C5/06 ,  G11C8/16

CPC classification number: G11C8/16 ,  G11C5/063

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract translation: 公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。 因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。