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    FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME
    31.
    发明申请
    FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME 有权
    FLASH存储器件，编程和读取方法

    公开(公告)号：US20110038207A1

    公开(公告)日：2011-02-17

    申请号：US12856698

    申请日：2010-08-16

    Applicant: Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

    Inventor： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

    IPC: G11C16/04

    CPC classification number: G11C11/5628 ,  G11C11/5642

    Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

    Abstract translation: 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

    PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER
    33.
    发明申请
    PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER 有权
    PAGE-BUFFER和非易失性半导体存储器，包括页面缓冲区

    公开(公告)号：US20100202204A1

    公开(公告)日：2010-08-12

    申请号：US12752213

    申请日：2010-04-01

    Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

    Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

    IPC: G11C16/04 ,  G11C7/10

    CPC classification number: G11C16/0483 ,  G11C16/26

    Abstract: In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

    Abstract translation: 在一个方面，提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

    BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE
    35.
    发明申请
    BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE 有权
    用于增强闪存存储器件的可靠性的偏置电路和方法

    公开(公告)号：US20100067297A1

    公开(公告)日：2010-03-18

    申请号：US12571980

    申请日：2009-10-01

    Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

    Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

    IPC: G11C16/26 ,  G11C16/04

    CPC classification number: G11C8/08 ,  G11C16/349

    Abstract: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

    Abstract translation: 非易失性半导体存储器件包括：连接到相应位线的单元串; 每个单元串具有连接到串选择线的串选择晶体管，连接到接地选择线的接地选择晶体管和连接到对应字线并且串联连接在串选择晶体管和接地选择晶体管之间的存储单元 ; 第一电压降电路，被配置为在读取操作期间减小施加的读取电压; 配置为减小所施加的读取电压的第二电压降电路; 串行选择线驱动电路，被配置为利用由第一压降电路提供的降低的电压驱动串选择线; 以及接地选择线驱动电路，被配置为用由第二压降电路提供的降低的电压来驱动接地选择线。

    PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER
    36.
    发明申请
    PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER 有权
    PAGE-BUFFER和非易失性半导体存储器，包括页面缓冲区

    公开(公告)号：US20090296494A1

    公开(公告)日：2009-12-03

    申请号：US12035028

    申请日：2008-02-21

    Applicant: Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

    Inventor： Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

    IPC: G11C7/10

    CPC classification number: G11C16/0483 ,  G11C16/26

    Abstract: In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

    Abstract translation: 在一个方面，提供可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

    Memory device and memory programming method
    37.
    发明申请
    Memory device and memory programming method 有权
    存储器和存储器编程方法

    公开(公告)号：US20090296486A1

    公开(公告)日：2009-12-03

    申请号：US12382351

    申请日：2009-03-13

    Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

    Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

    IPC: G11C16/06

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

    Abstract: Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

    Abstract translation: 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

    MEMORY SYSTEM THAT USES AN INTERLEAVING SCHEME AND A METHOD THEREOF
    38.
    发明申请
    MEMORY SYSTEM THAT USES AN INTERLEAVING SCHEME AND A METHOD THEREOF 有权
    使用交互方案的记忆系统及其方法

    公开(公告)号：US20090150751A1

    公开(公告)日：2009-06-11

    申请号：US12256784

    申请日：2008-10-23

    Applicant: Nam Phil Jo ,  Dong Hyuk Chae ,  Sung Chung Park ,  Dong Gu Kang

    Inventor： Nam Phil Jo ,  Dong Hyuk Chae ,  Sung Chung Park ,  Dong Gu Kang

    IPC: G06F12/00 ,  H03M13/05 ,  G06F11/10

    CPC classification number: G11C7/1042 ,  G06F11/1068 ,  G06F13/4239

    Abstract: A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.

    Abstract translation: 存储器系统包括多个存储器件，被配置为控制多个存储器件的控制器以及连接在多个存储器件与控制器之间的至少一个通道。 所述至少一个通道包括与所述多个存储器件连接的输入/输出数据线和控制信号线以及分别连接到所述多个存储器件中的每一个的芯片使能信号线，其中所述芯片使能信号线使得能够 多个存储设备独立。 控制器向多个存储器件之一发送读取命令或程序命令，并且当多个存储器件中的一个存储器件响应于读取命令执行内部读取操作时，控制器从另一个 多个存储器件，或者当多个存储器件中的一个存储器件响应于程序命令执行内部程序操作时，控制器将数据编程到多个存储器件中的另一个。

    Apparatus and method for multi-bit programming
    39.
    发明申请
    Apparatus and method for multi-bit programming 审中-公开
    多位编程的装置和方法

    公开(公告)号：US20090046510A1

    公开(公告)日：2009-02-19

    申请号：US12007775

    申请日：2008-01-15

    Applicant: Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    Inventor： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC: G11C7/10

    CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    Abstract: Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.

    Abstract translation: 提供了多位编程设备和方法。 一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。 由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

    NONVOLATILE MEMORY DEVICE AND METHODS OF PROGRAMMING AND READING THE SAME
    40.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHODS OF PROGRAMMING AND READING THE SAME 有权
    非易失性存储器件及其编程和读取方法

    公开(公告)号：US20080310234A1

    公开(公告)日：2008-12-18

    申请号：US12136150

    申请日：2008-06-10

    Applicant: Seung-Jae LEE ,  Dong-Hyuk CHAE ,  Dong-Ku KANG

    Inventor： Seung-Jae LEE ,  Dong-Hyuk CHAE ,  Dong-Ku KANG

    IPC: G11C16/06 ,  G11C7/00

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C2216/14

    Abstract: A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and the current threshold voltage value to calculate a shifted threshold voltage level of the index cell. A read voltage is changed by the shifted threshold voltage level to read user data using the changed read voltage.

    Abstract translation: 非易失性存储器件的读取方法包括从存储指示初始阈值电压的信息的阈值电压信息单元读取索引单元的初始阈值电压值，从索引单元确定当前阈值电压值，以及比较初始值 阈值电压值和电流阈值电压值，以计算索引单元的偏移阈值电压电平。 读取电压由偏移的阈值电压电平改变，以便使用改变的读取电压来读取用户数据。

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