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公开(公告)号：US20090323445A1
公开(公告)日：2009-12-31
申请号：US12146777
申请日：2008-06-26
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C11/41 , G11C29/1201
摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.
摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。 该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过 在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。
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32.发明申请IMPLEMENTING LOW POWER LEVEL SHIFTER FOR HIGH PERFORMANCE INTEGRATED CIRCUITS 审中-公开实现高性能集成电路的低功率电平变换器公开(公告)号：US20090174457A1
公开(公告)日：2009-07-09
申请号：US11970624
申请日：2008-01-08
IPC分类号： H03L5/00
CPC分类号： H03K3/356165 , H03K3/012
摘要： A low power level shifter circuit for high performance integrated circuits includes an input inverter operating in a domain of a first voltage supply and receiving an input signal and a design structure on which the subject circuit resides is provided. An output stage operating in a domain of a higher second voltage supply includes a first output inverter connected to the input inverter and a second output inverter connected in series with the first output inverter. The second output inverter provides a level shifted output signal having a voltage level corresponding to the second voltage supply. A series connected finisher transistor and finisher control transistor are connected between the second voltage supply and an input to the first output inverter. The finisher control transistor is activated responsive to the input signal. A path control transistor controls a path between the first voltage supply and the input inverter. The path control transistor being activated responsive to the level shifted output signal.
摘要翻译： 用于高性能集成电路的低功率电平移位器电路包括在第一电压源的区域中操作并接收输入信号的输入反相器和设置有被摄体电路的设计结构。 在较高的第二电压源的区域中工作的输出级包括连接到输入反相器的第一输出反相器和与第一输出反相器串联连接的第二输出反相器。 第二输出反相器提供具有对应于第二电压源的电压电平的电平移位输出信号。 串联连接的整流晶体管和整流器控制晶体管连接在第二电压源和与第一输出反相器的输入端之间。 整理器控制晶体管响应于输入信号被激活。 路径控制晶体管控制第一电压源和输入反相器之间的路径。 路径控制晶体管响应于电平移位的输出信号被激活。
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公开(公告)号：US07525367B2
公开(公告)日：2009-04-28
申请号：US11538967
申请日：2006-10-05
IPC分类号： H04L5/00
CPC分类号： H03K19/094 , H03K19/018521
摘要： A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.
摘要翻译： 低功率电平移位器电路包括在第一电压源的域中操作的输入反相器。 输入反相器接收输入信号并提供第一反相信号。 输出反相器，其在与输入反相器耦合的第二电压源的区域中工作，并提供具有与第二电压源相对应的电压电平的输出信号和对应于输入信号的逻辑值。 第二电压源高于第一电压源。 泄漏电流控制电路包括连接在第二电压源和输出反相器的输入端之间的整流晶体管，并且路径控制晶体管控制第一电压源与输入反相器之间的路径。
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公开(公告)号：US07505340B1
公开(公告)日：2009-03-17
申请号：US11845866
申请日：2007-08-28
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： 一种方法实现了静态随机存取存储器（SRAM）单元写入性能评估。 SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。
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35.发明申请Method and Apparatus for Implementing SRAM Cell Write Performance Evaluation 失效实现SRAM单元写入性能评估的方法和装置公开(公告)号：US20090063912A1
公开(公告)日：2009-03-05
申请号：US11873173
申请日：2007-10-16
IPC分类号： G11C29/08
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： 一种用于实现静态随机存取存储器（SRAM）单元写入性能评估的方法和装置，以及设置有主题电路所在的设计结构。 ASRAM内核包括只连接到一个位列的每个字线。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。
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36.发明申请METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效用于实现SRAM单元写性能评估的方法和装置公开(公告)号：US20090059697A1
公开(公告)日：2009-03-05
申请号：US11845866
申请日：2007-08-28
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。
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37.发明申请ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED NUMBER OF REDUNDANT ELEMENTS 审中-公开增强SRAM冗余电路，用于减少接线和需要的冗余元件数量公开(公告)号：US20080273406A1
公开(公告)日：2008-11-06
申请号：US12172318
申请日：2008-07-14
CPC分类号： G11C29/846
摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.
摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。
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公开(公告)号：US07443744B2
公开(公告)日：2008-10-28
申请号：US11559431
申请日：2006-11-14
IPC分类号： G11C7/00
CPC分类号： G11C29/846
摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.
摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。
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39.发明授权公开(公告)号：US07283411B2
公开(公告)日：2007-10-16
申请号：US11552791
申请日：2006-10-25
IPC分类号： G11C7/00
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。 洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。 通过开始正常的写操作来引发洪泛模式。 在新的数据值被强制进入SRAM单元之后，写入信号被切断。 延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。 在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。
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