公开(公告)号：US20050104206A1

公开(公告)日：2005-05-19

申请号：US10988390

申请日：2004-11-12

申请人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

发明人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

IPC分类号： H01L25/10 ,  G11C5/00 ,  H01L21/50 ,  H01L23/48 ,  H01L25/18 ,  H05K1/18

CPC分类号： H05K1/181 ,  H01L2924/0002 ,  H05K2201/097 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.

摘要翻译： 本发明的实施例可以包括用于高密度安装的集成电路模块结构。 一个实施例可以包括布线​​板，具有在其至少一个表面上具有沿第一方向确定的安装长度的安装长度和在第二方向上确定的安装宽度的安装空间以及具有封装安装组合的多个集成电路封装 长度比布线板的安装长度长。 实施例还可以在直接安装在安装空间上的多个集成电路封装中具有一些封装，而其他封装间接安装在安装空间上。 本实施例可以具有水平和垂直地彼此重叠的封装。 即使在集成电路芯片或封装尺寸增加时，实施例允许多个芯片或封装被安装在有限的区域中而不改变集成电路模块的外形尺寸。

公开(公告)号：US06870742B2

公开(公告)日：2005-03-22

申请号：US10200731

申请日：2002-07-22

申请人： Myun-Joo Park ,  Byung-Se So ,  Sang-Won Lee ,  Jae-Jun Lee

发明人： Myun-Joo Park ,  Byung-Se So ,  Sang-Won Lee ,  Jae-Jun Lee

IPC分类号： G06F1/18 ,  G06F3/06 ,  G06F13/14 ,  H05K1/02 ,  H05K7/06

CPC分类号： H05K1/0248 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254

摘要： A system board includes a control unit; connectors arranged in series in one direction and accepting a connecting means for inputting and outputting data; and signal lines connecting the control unit to the connectors and including at least one branch point, wherein sub signal lines branched off at the same branch point are equal in length and/or loads of path from the branch point to the connecting means.

摘要翻译： 系统板包括控制单元; 连接器在一个方向上串联布置并且接受用于输入和输出数据的连接装置; 以及将控制单元连接到连接器并且包括至少一个分支点的信号线，其中在相同分支点处分支的子信号线在从分支点到连接装置的路径的长度和/或负载相等。

公开(公告)号：US20050002241A1

公开(公告)日：2005-01-06

申请号：US10837610

申请日：2004-05-04

申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

IPC分类号： G06F12/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06

CPC分类号： G06F13/4086

摘要： A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.

摘要翻译： 存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。 该系统还包括连接到存储器总线之间的存储器控​​制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。 虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

公开(公告)号：US06772262B1

公开(公告)日：2004-08-03

申请号：US09777446

申请日：2001-02-06

申请人： Myun-joo Park ,  Byung-se So

发明人： Myun-joo Park ,  Byung-se So

IPC分类号： G11C800

CPC分类号： H05K1/0216 ,  G06F13/1684 ,  G11C5/04 ,  G11C5/06 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2203/1572

摘要： A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

公开(公告)号：US08051343B2

公开(公告)日：2011-11-01

申请号：US12926043

申请日：2010-10-22

申请人： Seung-Man Shin ,  Byung-Se So ,  Seung-Jin Seo ,  You-Keun Han

发明人： Seung-Man Shin ,  Byung-Se So ,  Seung-Jin Seo ,  You-Keun Han

IPC分类号： G11C29/00

CPC分类号： G11C29/08 ,  G11C5/04 ,  G11C2029/5602

摘要： Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

摘要翻译： 示例性实施例涉及一种测试存储器模块的方法和系统，该存储器模块具有经由差分输入端子接收单端输入信号的过程，通过该差分输入端子可以从测试设备接收分组信号的差分对，其中测试设备的多个终端 可以与存储器模块的多个端子不同，并且基于单端输入信号测试存储器模块的存储器芯片。

公开(公告)号：US07849373B2

公开(公告)日：2010-12-07

申请号：US12285149

申请日：2008-09-30

申请人： Seung-Man Shin ,  Byung-Se So ,  Seung-Jin Seo ,  You-Keun Han

发明人： Seung-Man Shin ,  Byung-Se So ,  Seung-Jin Seo ,  You-Keun Han

IPC分类号： G11C29/00

CPC分类号： G11C29/08 ,  G11C5/04 ,  G11C2029/5602

摘要： Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

摘要翻译： 示例性实施例涉及一种测试存储器模块的方法和系统，该存储器模块具有经由差分输入端子接收单端输入信号的过程，通过该差分输入端子可以从测试设备接收分组信号的差分对，其中测试设备的多个终端 可以与存储器模块的多个端子不同，并且基于单端输入信号测试存储器模块的存储器芯片。

公开(公告)号：US07847383B2

公开(公告)日：2010-12-07

申请号：US11797592

申请日：2007-05-04

申请人： Byung-Se So ,  Dong-Ho Lee

发明人： Byung-Se So ,  Dong-Ho Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The input/output pad of the first semiconductor chip directly receives an input/output signal via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

摘要翻译： 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一半导体芯片的输入/输出焊盘通过多芯片封装的相应引脚直接接收输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。

公开(公告)号：US07606110B2

公开(公告)日：2009-10-20

申请号：US11029008

申请日：2005-01-05

申请人： You-Keun Han ,  Hui-Chong Shin ,  Seung-Jin Seo ,  Byung-Se So ,  Young-Man Ahn ,  Seung-Man Shin ,  Jung-Kuk Lee ,  Ho-Suk Lee

发明人： You-Keun Han ,  Hui-Chong Shin ,  Seung-Jin Seo ,  Byung-Se So ,  Young-Man Ahn ,  Seung-Man Shin ,  Jung-Kuk Lee ,  Ho-Suk Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/04 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/401 ,  G11C29/12015 ,  G11C29/14

摘要： A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

摘要翻译： 存储器模块，存储器单元和具有非周期性时钟的集线器及其使用方法。 示例性存储器模块可以包括相位锁定环路，接收外部周期性时钟并且生成一个或多个内部周期性时钟和多个存储器单元，从外部源接收内部周期性时钟之一或非周期性时钟。

公开(公告)号：US07350120B2

公开(公告)日：2008-03-25

申请号：US10833322

申请日：2004-04-28

申请人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jae-Jun Lee

发明人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jae-Jun Lee

IPC分类号： G11C29/00 ,  G01R31/02

CPC分类号： G11C29/48 ,  G11C2029/5602 ,  G11C2029/5606

摘要： A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.

摘要翻译： 缓冲存储器模块包括安装的缓冲电路和安装在板的第一表面上的多个存储器件，存储器件电连接到缓冲电路。 存储器模块还包括位于板的第二表面上并电连接到缓冲电路的多个测试焊盘。

公开(公告)号：US20070033457A1

公开(公告)日：2007-02-08

申请号：US11459887

申请日：2006-07-25

申请人： Sung-Joo PARK ,  Jae-Jun LEE ,  Byung-Se SO ,  Jung-Joon LEE

发明人： Sung-Joo PARK ,  Jae-Jun LEE ,  Byung-Se SO ,  Jung-Joon LEE

IPC分类号： G01R31/28

CPC分类号： H05K1/115 ,  H05K1/0237 ,  H05K3/0047 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/1476

摘要： A circuit board and a method of manufacturing the same are disclosed. Embodiments of the circuit board may include a dielectric substrate, a first via structure comprising a first via-hole, which is defined through the dielectric substrate, and a plurality of first vias that are formed on an inner wall of the first via-hole and to connect a plurality of signal patterns positioned on the upper and lower surfaces of the dielectric substrate.

摘要翻译： 公开了一种电路板及其制造方法。 电路板的实施例可以包括电介质基板，第一通孔结构，其包括通过电介质基板限定的第一通孔，以及形成在第一通孔的内壁上的多个第一通孔，以及 以连接位于电介质基板的上表面和下表面上的多个信号图案。