公开(公告)号：US06424196B2

公开(公告)日：2002-07-23

申请号：US09740269

申请日：2000-12-19

申请人： Alain Pomet

发明人： Alain Pomet

IPC分类号： H03K312

CPC分类号： G06K19/073 ,  H03K3/0372 ,  H03K3/35625

摘要： A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

摘要翻译： 主从D型触发器电路包括功率消耗掩蔽电路，其包括与触发器电路的主器件和从器件并联的参考级。 该结构有利地提供触发器电路在时钟信号的前沿和后沿的每个上的切换，用于触发器电路的排序。

公开(公告)号：US06230178B1

公开(公告)日：2001-05-08

申请号：US09190734

申请日：1998-11-12

申请人： Alain Pomet

发明人： Alain Pomet

IPC分类号： G06F772

CPC分类号： G06F7/535 ,  G06F7/728

摘要： A modular arithmetic coprocessor comprises a circuit for the computation of an error correction parameter H=2x mod N associated with the Montgomery method. This computation circuit comprises a first register, a second register, and a first circuit for the series subtraction of either zero, N, twice N, or three times N from the contents of the first register. A multiplication circuit carries out a multiplication by four. A second circuit compares the result with N, twice N or three times N.

摘要翻译： 模数算术协处理器包括用于计算与蒙​​哥马利方法相关联的纠错参数H = 2xmod N的电路。 该计算电路包括第一寄存器，第二寄存器和用于从第一寄存器的内容中串联减去零，N，两倍N或三倍N的第一电路。 乘法电路执行乘以4。 第二个电路将结果与N进行比较，两次N或三次N.

公开(公告)号：US5963505A

公开(公告)日：1999-10-05

申请号：US105560

申请日：1998-06-26

申请人： Alain Pomet ,  Bernard Plessier

发明人： Alain Pomet ,  Bernard Plessier

IPC分类号： G11C8/12 ,  G11C19/00 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C19/00

摘要： A sequential access memory working at the rate of a clock signal CK includes N register elements N, each storing an information bit. These register elements are divided into L groups, each comprising P elements that are series-connected and simultaneously activated or not activated (with P.times.L=N). The register elements of a given group are activated at least P times consecutively during a part of the time, and are not activated for the rest of the time. Accordingly, each group stores P consecutive information bits each from among the N bits arriving in serial form at the input of the memory. The advantage of the memory is that it enables a reduction in the dynamic energy consumption.

摘要翻译： 以时钟信号CK的速率工作的顺序存取存储器包括N个寄存器元件N，每个寄存器元件存储信息位。 这些寄存器元件分为L组，每组包括串联连接并同时激活或未激活的P元素（PxL = N）。 给定组的寄存器元件在一段时间内连续至少P次激活，并且在其余时间内不被激活。 因此，每个组在存储器的输入处以串行形式到达的N个比特中存储P个连续的信息比特。 存储器的优点在于其能够降低动态能量消耗。

公开(公告)号：US10810476B2

公开(公告)日：2020-10-20

申请号：US13387792

申请日：2010-07-30

申请人： Michel Thill ,  Alain Pomet

发明人： Michel Thill ,  Alain Pomet

IPC分类号： G06F3/00 ,  G06K19/077 ,  G06K7/10 ,  G06K19/07

摘要： The invention relates to an electronic circuit for interconnecting a smartcard chip with a peripheral device, comprising: —a dedicated communication interface adapted to communicate with a smartcard chip; —a configurable communication interface adapted to communicate with a peripheral device; —a configuration module adapted to receive on said dedicated communication interface a request for configuring the configurable communication interface, adapted to configure the communication protocol of the configurable communication interface with the peripheral device based on the received request; —a bridging module adapted for converting data exchanged between the peripheral device and the smartcard chip through the dedicated communication interface and the configurable communication interface.

公开(公告)号：US08412873B2

公开(公告)日：2013-04-02

申请号：US12809898

申请日：2007-12-21

申请人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

发明人： Robert Leydier ,  Alain Pomet ,  Benjamin Duval

IPC分类号： G06F13/36 ,  G06F13/20

CPC分类号： G06F13/4027

摘要： A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

摘要翻译： 桥电路10设置在第一数据端口A1，A2和第二数据端口B1，B2之间。 桥接电路包括第一收发器级40，其包括至少一个输入缓冲器11,14和与第一数据端口链接的至少一个三态输出缓冲器12,13;第二收发器级50，包括至少一个输入缓冲器21， 24和连接到第二数据端口的至少一个三态输出缓冲器12,13，用于检测第一数据端口到达分组的第一检测电路31，用于检测分组到达的第二检测电路37 由第二个数据端口。 选择电路34,35可以根据由第一和第二检测电路进行的检测来输出第一或第二收发器级的三态输出缓冲器。

公开(公告)号：US20120131234A1

公开(公告)日：2012-05-24

申请号：US13387792

申请日：2010-07-30

申请人： Michel Thill ,  Alain Pomet

发明人： Michel Thill ,  Alain Pomet

IPC分类号： G06F3/00

CPC分类号： G06K19/077 ,  G06K7/10247 ,  G06K19/07 ,  G06K19/07733

摘要： The invention relates to an electronic circuit (3) for interconnecting a smartcard chip with a peripheral device, comprising:—a dedicated communication interface (31) adapted to communicate with a smartcard chip;—a configurable communication interface (33,34,35) adapted to communicate with a peripheral device;—a configuration module (32) adapted to receive on said dedicated communication interface a request for configuring the configurable communication interface, adapted to configure the communication protocol of the configurable communication interface with the peripheral device based on the received request;—a bridging module (32) adapted for converting data exchanged between the peripheral device and the smartcard chip through the dedicated communication interface and the configurable communication interface.

摘要翻译： 本发明涉及一种用于将智能卡芯片与外围设备互连的电子电路（3），包括：适于与智能卡芯片通信的专用通信接口（31）; - 可配置通信接口（33,34,35） 适于与外围设备进行通信; - 配置模块（32），其适于在所述专用通信接口上接收关于配置所述可配置通信接口的请求，其适于根据所述外围设备配置与所述外围设备的所述可配置通信接口的通信协议 接收请求; - 桥接模块（32），其适于通过所述专用通信接口和所述可配置通信接口来转换在所述外围设备和所述智能卡芯片之间交换的数据。

公开(公告)号：US07958175B2

公开(公告)日：2011-06-07

申请号：US11653185

申请日：2007-01-12

申请人： Alain Pomet ,  Benjamin Duval ,  Robert Leydier

发明人： Alain Pomet ,  Benjamin Duval ,  Robert Leydier

IPC分类号： G06F1/02

CPC分类号： G06F7/588

摘要： A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

摘要翻译： 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。

公开(公告)号：US20090089347A1

公开(公告)日：2009-04-02

申请号：US11653185

申请日：2007-01-12

申请人： Alain Pomet ,  Benjamin Duval ,  Robert Leydier

发明人： Alain Pomet ,  Benjamin Duval ,  Robert Leydier

IPC分类号： G06F7/58

CPC分类号： G06F7/588

摘要： A method for generating a random number, comprising steps of receiving a data transmission binary signal subjected to phase jitter, generating several oscillator signals substantially of a same average frequency and having distinct respective phases, sampling a status of each of the oscillator signals upon the appearance of edges of the binary signal, and of generating a random number using the statuses of each of the oscillator signals. The method may be applied to an integrated circuit usable in a smart card.

摘要翻译： 一种用于产生随机数的方法，包括以下步骤：接收经历相位抖动的数据传输二进制信号，产生基本上具有相同平均频率的几个振荡器信号，并具有不同的相位，在出现时对每个振荡器信号的状态进行采样 的二进制信号的边沿，并且使用每个振荡器信号的状态来产生随机数。 该方法可以应用于可用于智能卡的集成电路。

公开(公告)号：US07319758B2

公开(公告)日：2008-01-15

申请号：US09727300

申请日：2000-11-30

申请人： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

发明人： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

IPC分类号： H04L9/00 ,  G06F11/30 ,  G06F1/04 ,  G06F3/00

CPC分类号： H04L9/0891 ,  H04L9/0631 ,  H04L2209/04

摘要： In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

摘要翻译： 在包括双向总线的电子部件中，数据元件通过该双向总线以时钟信号的速率在外围设备和中央处理单元之间行进，中央处理单元和至少一个外围设备都包括数据加密/解密单元。 每个数据加密/解密单元使用相同的秘密密钥。 秘密密钥是从与时钟信号同步的随机信号在每个小区中的每个时钟周期本地产生的，并且通过单向传输线应用于每个小区。

公开(公告)号：US20070106825A1

公开(公告)日：2007-05-10

申请号：US11462110

申请日：2006-08-03

申请人： Benjamin Duval ,  Alain Pomet

发明人： Benjamin Duval ,  Alain Pomet

IPC分类号： G06F13/42

CPC分类号： G06F13/4081

摘要： A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.

摘要翻译： 一个设备包括一个串行端口，用于通过串行链路作为从设备连接到主设备。 该装置还包括检测电路，用于检测与串行端口的端子相连接的主设备的阻抗的存在。 该设备可以与包含USB端口的微处理器卡一起使用。