公开(公告)号：US20010048340A1

公开(公告)日：2001-12-06

申请号：US09789198

申请日：2001-02-20

Inventor： Ting-Wah Wong

IPC: G05F003/02 ,  G05F001/10

CPC classification number: H01L21/823857 ,  H01L21/823892 ,  H01L27/0928

Abstract: A radio frequency device may be formed which has high power output and high transistor switching speeds. This may be done by providing thicker gate oxides and a higher supply potential to transistors utilized to form the power amplifier and using thinner gate oxides conventionally associated with high switching speed and advanced process technologies for other applications on the same integrated circuit. Thus, high switching speeds can be achieved with some transistors which utilize a lower supply voltage and high power output can be achieved from other transistors which are coupled to a higher supply voltage. The different types of transistors may be made in the same integrated circuit fabrication process on the same integrated circuit.

Abstract translation: 可以形成具有高功率输出和高晶体管切换速度的射频装置。 这可以通过为用于形成功率放大器的晶体管提供更厚的栅极氧化物和更高的电源电位，并且使用通常与高开关速度相关联的较薄栅极氧化物和用于同一集成电路上的其它应用的先进工艺技术来实现。 因此，可以通过利用较低电源电压和高功率输出的一些晶体管实现高切换速度，其可以与耦合到更高电源电压的其它晶体管实现。 不同类型的晶体管可以在同一集成电路上的相同集成电路制造工艺中制造。

公开(公告)号：US20010043114A1

公开(公告)日：2001-11-22

申请号：US09297867

申请日：1999-11-04

Inventor： GORAN MARNFELDT

IPC: G05F003/02

CPC classification number: H01L28/40 ,  H01L29/94 ,  H02M3/07

Abstract: A capacitor structure for an integrated circuit, the structure including a main capacitor and a parasitic capacitor, comprising: a substrate 2000 of a first conductivity type; a first dielectric layer 2040; a first conductive layer 2010 disposed over the first dielectric layer 2040, said first conductive layer 2010 forming a first plate of the main capacitor and a first plate of the parasitic capacitor; a second dielectric layer 2020 disposed over the first conductive layer 2010; and a second conductive layer 2030 disposed over the second dielectric layer 2020, the second conductive layer 2030 forming a second plate of the main capacitor; characterized in that the capacitor structure further comprises a well 2100 disposed within the substrate 2000 which is of a second conductivity type opposite to said first type, the first dielectric layer 2040 is disposed over the well 2100 and the well 2100 forms a second plate of the parasitic capacitor and a further, junction capacitor with the substrate 2000, the configuration being such that the parasitic and junction capacitors are mutually in series and in series with the main capacitor such as to reduce stray capacitance.

Abstract translation: 一种用于集成电路的电容器结构，所述结构包括主电容器和寄生电容器，包括：第一导电类型的衬底2000; 第一电介质层2040; 设置在第一介电层2040上的第一导电层2010，形成主电容器的第一板的第一导电层2010和寄生电容器的第一板; 设置在第一导电层2010上的第二电介质层2020; 以及设置在第二介电层2020上的第二导电层2030，第二导电层2030形成主电容器的第二板; 其特征在于，电容器结构还包括设置在衬底2000内的阱2100，其具有与所述第一类型相反的第二导电类型，第一电介质层2040设置在阱2100上，并且阱2100形成第二板 寄生电容器和另一个具有衬底2000的结电容器，其结构使得寄生和结电容器彼此串联并与主电容器串联，以减少杂散电容。

公开(公告)号：US20010030571A1

公开(公告)日：2001-10-18

申请号：US09823328

申请日：2001-03-29

Inventor： Yusuke Tsutsui ,  Makoto Kitagawa ,  Mitsugu Kobayashi ,  Hisao Uehara

IPC: G05F003/02

CPC classification number: H02M1/36 ,  G09G3/3696 ,  H02M3/07

Abstract: A driving circuit of a display device such as a liquid crystal generates power supply clocks (1 and 2) based on a system clock during the normal display operation which is not a power save mode. The generated power supply clocks are supplied, directly or after inversion, to the switches (SW1 through SW4 (and SW5 through SW8)) in a charge pump type power supply circuit (300) for switching the connection of capacitors (C1 and C2 (and C11 and C12)) in the power supply circuit (300). In this manner, supply voltages VDD2 and VDD3 which function as the driving power supply for a driving circuit (100) and a display panel (200) can be obtained at the power supply circuit (300) by boosting the input voltage Vin. The driving circuit (100) stops supply of the power supply clocks to the power supply circuit (300) when a transition to the power save mode is instructed and a power save control signal generated by a CPU I/F circuit (16) is changed, thereby suspending generation of the supply voltage an consumption of power consumption at the circuit and display panel.

Abstract translation: 诸如液晶的显示装置的驱动电路在不是省电模式的正常显示操作期间基于系统时钟产生电源时钟（1和2）。 所产生的电源时钟在电荷泵式电源电路（300）中直接或倒置后供给开关（SW1至SW4（和SW5至SW8）），用于切换电容器（C1和C2（和 C11和C12））。 以这种方式，通过升压输入电压Vin，可以在电源电路（300）获得用作驱动电路（100）和显示面板（200）的驱动电源的电源电压VDD2和VDD3。 驱动电路（100）在指示向省电模式的转变时停止向电源电路（300）供给电源时钟，并且由CPU I / F电路（16）产生的省电控制信号发生变化 从而暂停生成电源电压消耗电路和显示面板的功耗。

公开(公告)号：US20010007517A1

公开(公告)日：2001-07-12

申请号：US09783583

申请日：2001-02-15

Applicant: Rohm Co. Ltd.

Inventor： Akio Fujikawa

IPC: G11B005/02 ,  G05F003/02

CPC classification number: G11B5/012

Abstract: A semiconductor integrated circuit device for a magnetic disk apparatus has analog circuits such as a read/write circuit and digital circuits such as an interface driver circuit, a control circuit, and a stepping motor driver circuit, all of these circuits operating on a single supply voltage. The semiconductor integrated circuit device further has a voltage regulator whose output voltage is lower than the supply voltage and variable according to the voltage applied to an output voltage adjustment terminal. The control circuit operates on the output voltage of this regulator.

Abstract translation: 一种用于磁盘装置的半导体集成电路装置具有诸如读/写电路和诸如接口驱动电路，控制电路和步进电机驱动电路的数字电路的模拟电路，所有这些电路都在单个电源 电压。 半导体集成电路装置还具有输出电压低于电源电压并根据施加到输出电压调整端子的电压而变化的电压调节器。 控制电路对该稳压器的输出电压进行工作。

公开(公告)号：US20040263240A1

公开(公告)日：2004-12-30

申请号：US10609513

申请日：2003-06-30

Applicant: Intel Corporation

Inventor： Robert Fulton ,  Andrew Volk ,  Chinnugounder Senthilkumar

IPC: G05F003/02

CPC classification number: G05F1/56

Abstract: According to an embodiment of the invention, a method and apparatus for dynamic reference voltage adjustment are described. According to one embodiment, a reference circuit comprises a reference node to provide a reference voltage; a first transistor device to receive a first configuration signal at a gate terminal, a current to flow through the first transistor device when the first configuration signal is a first value; and a second transistor device to receive a first voltage potential at a gate terminal, the current to flow through the second transistor device and the reference voltage to be increased by the first voltage potential when the configuration signal is a second value.

Abstract translation: 根据本发明的实施例，描述了用于动态参考电压调整的方法和装置。 根据一个实施例，参考电路包括用于提供参考电压的参考节点; 第一晶体管器件，用于在栅极端子处接收第一配置信号;当第一配置信号是第一值时，流过第一晶体管器件的电流; 以及第二晶体管器件，用于在栅极端子处接收第一电压电势，当配置信号为第二值时，流过第二晶体管器件的电流和参考电压将被增加第一电压电位。

公开(公告)号：US20040222841A1

公开(公告)日：2004-11-11

申请号：US10604405

申请日：2003-07-17

Inventor： Hong-chin Lin ,  Nai-Hsien Chen ,  Jain-Hao Lu ,  Chien-Hung Ho

IPC: G05F003/02

CPC classification number: H02M3/073 ,  H02M2003/075 ,  H02M2003/078

Abstract: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.

Abstract translation: 电荷泵电路具有输入和输出节点，第一晶体管，第二晶体管，第三晶体管，第一电容器和第二电容器。 第一晶体管的漏极和第二晶体管的漏极连接到输入节点。 第二晶体管的源极和第三晶体管的漏极连接到输出节点。 第一电容器连接到第二晶体管的栅极。 第三晶体管连接到第二晶体管的衬底和源极。 当第一晶体管导通时，输入节点处的电压将对第一电容器充电。 当第二晶体管导通时，第三晶体管同时导通，使得基板和第二晶体管的源极将达到相同的电压电平。 然后，输入节点处的电压将对第二个电容器充电。

公开(公告)号：US20040183586A1

公开(公告)日：2004-09-23

申请号：US10732826

申请日：2003-12-09

Inventor： Seung-Hoon Lee ,  Jae-Yoon Sim

IPC: G05F003/02

CPC classification number: H02M3/07

Abstract: A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.

Abstract translation: 当外部电源电压高时，升压电路和产生升压电压的方法缓解由高电压应力引起的驱动晶体管的劣化。 升压电路包括升压电容器和开关。 升压电容器包括连接到驱动节点的第一升压电容器和输出升压电压的最后一个升压电容器。 开关响应于控制信号串联升压电容器。 随着驱动节点的电压电平根据升压电平控制信号的逻辑状态而改变，升压电压增加或减小。 升压电平控制信号响应于外部电源电压电平。 外部电源电压检测器检测外部电源电平的电平，并产生升压电平控制信号。

公开(公告)号：US20040178844A1

公开(公告)日：2004-09-16

申请号：US10782826

申请日：2004-02-23

Applicant: Oki Electric Industry Co., Ltd.

Inventor： Bunshou Kuramori

IPC: G05F003/02

CPC classification number: G05F3/242 ,  Y10T307/696

Abstract: An internal power supply circuit for a semiconductor integrated circuit includes two constant voltage generators having identical circuit topologies but generating two different constant voltages from an external power supply voltage. The lower constant voltage is selected when the external power supply voltage is below a predetermined level, the higher constant voltage is selected when the external power supply voltage is above the predetermined level, and an internal power supply voltage is generated from the selected constant voltage. The internal power supply voltage is stable over a wide flat region, but can also be raised to a higher level for stress testing of the semiconductor integrated circuit, and the higher level is also stable.

Abstract translation: 一种用于半导体集成电路的内部电源电路包括具有相同电路拓扑但由外部电源电压产生两个不同恒定电压的两个恒压发生器。 当外部电源电压低于预定电平时选择较低的恒定电压，当外部电源电压高于预定电平时选择较高的恒定电压，并从所选择的恒定电压产生内部电源电压。 内部电源电压在宽的平坦区域内是稳定的，但也可以升高到更高的水平，用于半导体集成电路的应力测试，而较高的电平也是稳定的。

公开(公告)号：US20040174207A1

公开(公告)日：2004-09-09

申请号：US10384231

申请日：2003-03-06

Inventor： Ivan Vandewege

IPC: G05F001/10 ,  G05F003/02

CPC classification number: H02M1/32 ,  H02H9/08

Abstract: An electronic device of one embodiment of the invention is disclosed which includes one or more wired interconnection points and a blocking mechanism. The one or more wired interconnection points are to interconnect to other electronic devices. The blocking mechanism is situated at the one or more wired interconnect points to reduce leakage current transferred from the other electronic devices over the one or more wired interconnection points.

公开(公告)号：US20040174206A1

公开(公告)日：2004-09-09

申请号：US10739969

申请日：2003-12-18

Inventor： Atsuko Matsumura

IPC: G05F001/10 ,  G05F003/02

CPC classification number: G05F1/46

Abstract: In order to solve a problem that during rise of an input voltage Vin, when the input voltage Vin exceeds a level of Vdetnull, but does not yet exceed a level of Vdetnull, no release signal is outputted, there is provided a voltage detecting circuit which is capable of removing a hysteresis voltage during the rise of the voltage Vin to output a release signal even in a case where the voltage Vin exceeds Vdetnull, but does not yet exceed Vdetnull.

Abstract translation: 为了解决在输入电压Vin上升的问题，当输入电压Vin超过Vdet-的电平但不超过Vdet +的电平时，不输出释放信号，所以提供电压检测电路 即使在电压Vin超过Vdet-甚至不超过Vdet +的情况下，也能够在电压Vin上升期间去除滞后电压以输出释放信号。