公开(公告)号：US08058895B1

公开(公告)日：2011-11-15

申请号：US12799366

申请日：2010-04-23

Applicant: Gautham Devendra Kamath

Inventor： Gautham Devendra Kamath

IPC: H03K17/16

CPC classification number: F17C13/002 ,  F17C13/005 ,  H03K19/1733

Abstract: A method of programming an integrated circuit to operate in a selected operating mode includes assigning different resistance values to correspond to different operating modes of the integrated circuit, wherein the different resistance values are non-zero finite values. The integrated circuit is programmed to operate in one of the modes based on a corresponding one of the different resistance values presented to a terminal of the integrated circuit.

Abstract translation: 编程集成电路以选择的操作模式操作的方法包括分配不同的电阻值以对应于集成电路的不同操作模式，其中不同的电阻值是非零有限值。 集成电路被编程为基于呈现给集成电路的端子的不同电阻值中的相应的一个，以模式之一工作。

公开(公告)号：US07982496B1

公开(公告)日：2011-07-19

申请号：US12417012

申请日：2009-04-02

Applicant: Steven P. Young

Inventor： Steven P. Young

IPC: H03K19/173

CPC classification number: H03K19/1733

Abstract: A bus-based logic block for an integrated circuit includes a provision for placing an arbitrary constant onto a data bus in the logic block. An exemplary logic block has multi-bit first and second inputs and a multi-bit output. The logic block includes a multi-bit multiplexer circuit, a multi-bit programmable logic circuit, and a constant generator circuit. The multiplexer circuit has a multi-bit first input coupled to a multi-bit first input of the logic block, a multi-bit second input, and a multi-bit output. The programmable logic circuit has a multi-bit first input coupled to the output of the multiplexer circuit, and a multi-bit output. The constant generator circuit has a multi-bit output coupled to the second input of the multiplexer circuit. Each bit of the logic block may be commonly controlled with all other bits of the logic block.

Abstract translation: 用于集成电路的基于总线的逻辑块包括用于将任意常数放置在逻辑块中的数据总线上的规定。 示例性的逻辑块具有多位第一和第二输入和多位输出。 逻辑块包括多位多路复用器电路，多位可编程逻辑电路和恒定的发生器电路。 多路复用器电路具有耦合到逻辑块的多位第一输入，多位第二输入和多位输出的多位第一输入。 可编程逻辑电路具有耦合到多路复用器电路的输出的多位第一输入和多位输出。 恒定发电机电路具有耦合到多路复用器电路的第二输入的多位输出。 逻辑块的每个位可以与逻辑块的所有其他位共同地被控制。

公开(公告)号：US07973563B2

公开(公告)日：2011-07-05

申请号：US12370163

申请日：2009-02-12

Applicant: Huan Huu Tran ,  Gregory Jon Richmond

Inventor： Huan Huu Tran ,  Gregory Jon Richmond

IPC: H03K19/094

CPC classification number: H03K19/1733 ,  H03K19/017581

Abstract: A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b) being configured as an input circuit which can be further configured to provide input logic switching level thresholds according to the configuration programming information, and (c) being configured as at least one output circuit which can be further configured to provide an output drive strength according to the configuration programming information.

Abstract translation: 耦合到集成电路的至少一个输入/输出端口的缓冲装置具有被配置为接收配置编程信息的多个控制输入。 所述至少一个输入/输出电路能够：（a）通过所述配置编程信息被配置为定向的通信感，（b）被配置为输入电路，所述输入电路可进一步被配置为提供输入逻辑切换电平阈值 根据所述配置编程信息，以及（c）被配置为至少一个输出电路，所述至少一个输出电路可进一步被配置为根据所述配置编程信息提供输出驱动强度。

公开(公告)号：US07924059B2

公开(公告)日：2011-04-12

申请号：US12394749

申请日：2009-02-27

Applicant: William L. Ditto ,  Krishnamurthy Murali ,  Sudeshna Sinha ,  Adi Bulsara

Inventor： William L. Ditto ,  Krishnamurthy Murali ,  Sudeshna Sinha ,  Adi Bulsara

IPC: H03K19/20

CPC classification number: H03K19/1733

Abstract: A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.

Abstract translation: 逻辑门适用于实现逻辑表达式。 逻辑门包括适于接收输入信号和至少一个控制信号的至少一个输入。 输入信号和控制信号中的至少一个是噪声信号。 至少一个输出适于产生输出信号。 非线性更新器作为动态可配置元件操作，并且至少部分地基于噪声信号产生由控制信号选择的多个不同的逻辑门。 非线性更新器电耦合到输入端并且还电耦合到输出端。 非线性更新被配置为响应于控制信号将非线性函数应用于输入信号，以产生表示由输入信号上的多个不同逻辑门之一实现的逻辑表达式的输出信号。

公开(公告)号：US07888979B2

公开(公告)日：2011-02-15

申请号：US12315024

申请日：2008-11-26

Applicant: Keun Kook Kim

Inventor： Keun Kook Kim

IPC: H03L7/00

CPC classification number: H03K19/1733 ,  G11C7/1051 ,  G11C7/1084 ,  G11C7/109 ,  G11C2207/105

Abstract: A pad input signal processing circuit includes a control unit for setting a level of a pad output terminal to which a first control signal is input in response to a power up signal, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal.

Abstract translation: 焊盘输入信号处理电路包括：控制单元，用于响应于上电信号设置输入第一控制信号的焊盘输出端子的电平;以及信号输出单元，用于响应于信号输出命令信号 和第二控制信号。

公开(公告)号：US07888971B2

公开(公告)日：2011-02-15

申请号：US12696755

申请日：2010-01-29

Applicant: Hiroaki Iwashita

Inventor： Hiroaki Iwashita

IPC: H03K19/096

CPC classification number: H03K19/1733 ,  G06F17/5031

Abstract: A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.

Abstract translation: 一种用于支持包括发射机时钟域和接收机时钟域的电路的逻辑验证的验证支持系统，发射机时钟域，系统包括用于接收要从发射机时钟域发射的数据的检测器，并且用于检测 由于响应于发射机时钟的任何定时波动而导致的接收数据。 该系统包括识别单元，用于识别由检测器确定的数据的任何波动是否基于接收数据的传播通过接收机时钟域的逻辑门中的至少一个传播到组合逻辑的输出 以组合逻辑来确定要输入到组合逻辑的数据的任何波动。

公开(公告)号：US20100219862A1

公开(公告)日：2010-09-02

申请号：US12394749

申请日：2009-02-27

Applicant: WILLIAM L. DITTO ,  Krishnamurthy Murali ,  Sudeshna Sinha ,  Adi Bulsara

Inventor： WILLIAM L. DITTO ,  Krishnamurthy Murali ,  Sudeshna Sinha ,  Adi Bulsara

IPC: H03K19/20

CPC classification number: H03K19/1733

Abstract: A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.

Abstract translation: 逻辑门适用于实现逻辑表达式。 逻辑门包括适于接收输入信号和至少一个控制信号的至少一个输入。 输入信号和控制信号中的至少一个是噪声信号。 至少一个输出适于产生输出信号。 非线性更新器作为动态可配置元件操作，并且至少部分地基于噪声信号产生由控制信号选择的多个不同的逻辑门。 非线性更新器电耦合到输入端并且还电耦合到输出端。 非线性更新被配置为响应于控制信号将非线性函数应用于输入信号，以产生表示由输入信号上的多个不同逻辑门之一实现的逻辑表达式的输出信号。

公开(公告)号：US07657862B2

公开(公告)日：2010-02-02

申请号：US11634462

申请日：2006-12-06

Applicant: Michael Kishinevsky ,  Jordi Cortadella

Inventor： Michael Kishinevsky ,  Jordi Cortadella

IPC: G06F17/50

CPC classification number: H03K19/1733 ,  G06F5/06 ,  G06F7/00 ,  G06F9/3869

Abstract: Embodiments of early enabling synchronous elastic designs, devices and methods are presented herein.

Abstract translation: 本文介绍了早期实现同步弹性设计，装置和方法的实施例。

公开(公告)号：US07610566B1

公开(公告)日：2009-10-27

申请号：US11754264

申请日：2007-05-25

Applicant: Andrew Caldwell ,  Steven Teig

Inventor： Andrew Caldwell ,  Steven Teig

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/504 ,  H03K19/1733

Abstract: Some embodiments provide a method of performing circuit synthesis that receives a design that has a function with several inputs. The method identifies a set of early arriving inputs of the function and performs a function decomposition on the function based on one of the early arriving inputs. In some embodiments, the method estimates the number of circuits a signal has to travel through to reach each input of the function and selects a set of inputs with signals that travel through fewer numbers of circuits compared to signals of inputs that are not selected. In some embodiments in which the design has more than a particular number of inputs, the method recursively identifies early arriving signals and performs function decomposition until function decomposition results in a set of functions all of which with fewer than the particular number of inputs. In some embodiments, the function decomposition is Shannon decomposition.

Abstract translation: 一些实施例提供一种执行电路合成的方法，其接收具有多个输入功能的设计。 该方法识别功能的一组早期到达输入，并且基于早期到达输入之一执行对该功能的功能分解。 在一些实施例中，该方法估计信号必须行进的电路数目以达到功能的每个输入，并且与没有选择的输入信号相比，选择一组输入，其中信号通过较少数量的电路行进。 在其中设计具有多于特定数量的输入的一些实施例中，该方法递归地识别提前到达的信号并执行功能分解，直到功能分解导致所有这些功能都小于特定数量的输入。 在一些实施例中，功能分解是香农分解。

公开(公告)号：US20090206875A1

公开(公告)日：2009-08-20

申请号：US12370163

申请日：2009-02-12

Applicant: Huan Huu Tran ,  Gregory Jon Richmond

Inventor： Huan Huu Tran ,  Gregory Jon Richmond

IPC: H03K19/173 ,  H03K19/0175

CPC classification number: H03K19/1733 ,  H03K19/017581

Abstract: A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b) being configured as an input circuit which can be further configured to provide input logic switching level thresholds according to the configuration programming information, and (c) being configured as at least one output circuit which can be further configured to provide an output drive strength according to the configuration programming information.

Abstract translation: 耦合到集成电路的至少一个输入/输出端口的缓冲装置具有被配置为接收配置编程信息的多个控制输入。 所述至少一个输入/输出电路能够：（a）通过所述配置编程信息被配置为定向的通信感，（b）被配置为输入电路，所述输入电路可进一步被配置为提供输入逻辑切换电平阈值 根据所述配置编程信息，以及（c）被配置为至少一个输出电路，所述至少一个输出电路可进一步被配置为根据所述配置编程信息提供输出驱动强度。