公开(公告)号：US4791600A

公开(公告)日：1988-12-13

申请号：US890192

申请日：1986-07-28

Applicant: Yih-Chyun Jenq

Inventor： Yih-Chyun Jenq

IPC: H04L27/00 ,  H03D7/00 ,  G06F7/52

CPC classification number: H03D7/00 ,  H03D2200/0056 ,  H03D2200/0072

Abstract: A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.

Abstract translation: 数字流水线外差电路包括用于产生m位数字系数的正弦和余弦函数发生器和用于将系数乘以数字化数据输入信号的m级数字乘法器。 三角形移位寄存器阵列将数字正弦和余弦函数发生器与乘法器级连接，并且通过在每个乘法器级延迟系数位的到达来提供在每个乘法器级同时处理输入数据的连续字节，以与一个 预定数据字节。 这在所有阶段同时进行，从而将处理时间减少了一个因子m。

公开(公告)号：US4130806A

公开(公告)日：1978-12-19

申请号：US799884

申请日：1977-05-23

Applicant: Petrus J. Van Gerwen ,  Rudolf A. Van Doorn ,  Wilfred A. M. Snijders ,  Hendrik A. Van Essen

Inventor： Petrus J. Van Gerwen ,  Rudolf A. Van Doorn ,  Wilfred A. M. Snijders ,  Hendrik A. Van Essen

IPC: H04L27/00 ,  H03D3/00 ,  H03D5/00 ,  H03D7/16 ,  H03H17/00 ,  H04L27/06 ,  H04B1/16

CPC classification number: H04L27/06 ,  H03D3/007 ,  H03D5/00 ,  H03D2200/0047 ,  H03D2200/0056 ,  H03D2200/006 ,  H03D2200/0082 ,  H03D7/165

Abstract: A digital filter and demodulation arrangement for passband signals, whose corresponding baseband signal has a bandwidth limited to a given maximum frequency. The passband signals are filtered according to two bandpass characteristics which, apart from their asymmetrical distortion relative to their central frequency, are versions from one another shifted 90.degree. in phase. The filtered passband signals are demodulated with an in-phase carrier and a quadrature carrier and the demodulated signals are combined to a baseband signal.In the digital filtering process the sampling frequency is reduced from a value higher than twice the highest frequency in the passband signals to a value which is not higher than twice said maximum frequency in the baseband signal and in the digital demodulation and combination processes the reduced sampling frequency is also used so that a considerable reduction in the internal processing speed is obtained.

Abstract translation: 用于通带信号的数字滤波器和解调装置，其相应的基带信号的带宽限制在给定的最大频率上。 根据两个带通特性对通带信号进行滤波，除了相对于它们的中心频率的不对称失真之外，它们的相位是相位相差90°。 滤波后的通带信号用同相载波和正交载波进行解调，解调后的信号与基带信号组合。