公开(公告)号：US06969425B2

公开(公告)日：2005-11-29

申请号：US10346887

申请日：2003-01-17

Applicant: Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

Inventor： Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/308 ,  H01L29/84 ,  C30B1/10

CPC classification number: B81C1/00365 ,  B81C2201/0164 ,  Y10T428/21 ,  Y10T428/2495

Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

公开(公告)号：US06770569B2

公开(公告)日：2004-08-03

申请号：US10210315

申请日：2002-08-01

Applicant: Juergen A. Foerstner ,  Steven M. Smith ,  Raymond Mervin Roop

Inventor： Juergen A. Foerstner ,  Steven M. Smith ,  Raymond Mervin Roop

IPC: H01L2131

CPC classification number: B81C1/0038 ,  B81B2201/018 ,  B81B2201/0292 ,  B81C1/00246 ,  B81C2201/0164 ,  B81C2203/0735 ,  H01G5/18

Abstract: A method is provided for making a MEMS structure (69). In accordance with the method, a CMOS substrate (51) is provided which has interconnect metal (53) deposited thereon. A MEMS structure is created on the substrate through the plasma assisted chemical vapor deposition (PACVD) of a material selected from the group consisting of silicon and silicon-germanium alloys. The low deposition temperatures attendant to the use of PACVD allow these materials to be used for MEMS fabrication at the back end of an integrated CMOS process.

Abstract translation: 提供了一种用于制造MEMS结构（69）的方法。 根据该方法，提供具有沉积在其上的互连金属（53）的CMOS基板（51）。 通过等离子体辅助化学气相沉积（PACVD）在由硅和硅 - 锗合金组成的组中选择的材料在衬底上产生MEMS结构。 使用PACVD的低沉积温度允许这些材料用于集成CMOS工艺后端的MEMS制造。

公开(公告)号：US06661070B2

公开(公告)日：2003-12-09

申请号：US10193804

申请日：2002-07-11

Applicant: Andrew J. Zosel ,  Joel A. Kubby ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Jingkuang Chen ,  Alex T. Tran

Inventor： Andrew J. Zosel ,  Joel A. Kubby ,  Peter M. Gulvin ,  Chuang-Chia Lin ,  Jingkuang Chen ,  Alex T. Tran

IPC: H01L2982

CPC classification number: B81C1/00666 ,  B81B2203/058 ,  B81C2201/014 ,  B81C2201/0164 ,  B81C2201/056 ,  G02B26/0833

Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a structure on a single crystal silicon layer separated by an insulator layer from a substrate layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; exposing a selected area of the single crystal silicon layer; and releasing the formed structure.

公开(公告)号：US20030138588A1

公开(公告)日：2003-07-24

申请号：US10334588

申请日：2002-12-30

Inventor： Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

IPC: B32B009/00

CPC classification number: B81C1/00365 ,  B81C2201/0164 ,  Y10T428/21 ,  Y10T428/2495

Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

Abstract translation: 公开了具有减小的平面外曲率的硼掺杂硅层。 这些层在顶部和底部表面附近具有基本相等的硼浓度。 由于相反的浓度基本相等，所以层上的压缩应力基本平衡，从而导致具有减小的面外曲率的层。

公开(公告)号：US20030124761A1

公开(公告)日：2003-07-03

申请号：US10263623

申请日：2002-10-03

Inventor： Kris Baert ,  Matty Caymax ,  Cristina Rusu ,  Sherif Sedky ,  Ann Witvrouw

IPC: H01L021/00

CPC classification number: H01L31/1804 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/017 ,  C23C16/22 ,  G01J5/20 ,  H01L31/09 ,  Y02E10/547 ,  Y02P70/521

Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1nullx layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Abstract translation: 获得沉积的多晶和低应力SiGe层的方法和设备。 这些层可以用于微机电系统（MEMS）装置或微加工结构中。 分析影响多晶层中的应力的不同参数。 参数包括但不限于：沉积温度; 半导体的浓度（例如，SixGe1-x层中的硅和锗的浓度，x是浓度参数）; 掺杂剂的浓度（例如硼或磷的浓度）; 压力量; 并使用等离子体。 取决于多晶SiGe生长的特定环境，可以使用不同的参数值。

公开(公告)号：US06503775B2

公开(公告)日：2003-01-07

申请号：US09956799

申请日：2001-09-21

Applicant: Satoru Nomoto ,  Masayoshi Takeuchi ,  Shuji Noda

Inventor： Satoru Nomoto ,  Masayoshi Takeuchi ,  Shuji Noda

IPC: H01L2100

CPC classification number: B81C1/00611 ,  B81C1/00365 ,  B81C2201/0122 ,  B81C2201/0164

Abstract: A production method of a micromachine includes a polysilicon film forming step which overlays grooves, defined in an upper surface of a sacrificial layer on a silicon substrate, with polysilicon layer so as to be flat. The production method includes a first processing step for filling the grooves by adding a lower laid portion of the polysilicon layer onto a sacrificial layer. The lower laid portion has a thickness greater than 0.625 times relative to a width of the grooves. The production method of the micromachine further includes a second processing step for making the polysilicon layer to have a predetermined thickness by adding a upper laid portion of the polysilicon layer on the lower laid portion to form the polysilicon layer, the upper laid portion formed by depositing polysilicon which has the same impurity concentration as the lower laid portion does.

公开(公告)号：US07046411B1

公开(公告)日：2006-05-16

申请号：US11118573

申请日：2005-04-29

Applicant: James G. Fleming

Inventor： James G. Fleming

IPC: H01H51/22 ,  G02B26/08

CPC classification number: B81B3/0032 ,  B81B2201/045 ,  B81B2203/053 ,  B81C2201/0164 ,  B81C2201/0167 ,  G02B26/0841 ,  Y10S359/904

Abstract: A microelectromechanical (MEM) apparatus is disclosed which includes one or more tensile-stressed actuators that are coupled through flexures to a stage on a substrate. The tensile-stressed actuators, which can be formed from tensile-stressed tungsten or silicon nitride, initially raise the stage above the substrate without any applied electrical voltage, and can then be used to control the height or tilt angle of the stage. An electrostatic actuator can also be used in combination with each tensile-stressed actuator. The MEM apparatus has applications for forming piston micromirrors or tiltable micromirrors and independently addressable arrays of such devices.

Abstract translation: 公开了一种微机电（MEM）装置，其包括一个或多个拉伸应力致动器，其通过挠曲件耦合到基板上的台。 可以由拉应力钨或氮化硅形成的拉伸应力致动器最初将基底升高到基板上方，而没有任何施加的电压，然后可用于控制载物台的高度或倾斜角度。 静电致动器也可以与每个拉伸应力致动器组合使用。 MEM装置具有用于形成活塞微镜或可倾斜的微反射镜以及这种装置的独立可寻址阵列的应用。

公开(公告)号：US06946200B2

公开(公告)日：2005-09-20

申请号：US10334588

申请日：2002-12-30

Applicant: Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

Inventor： Cleopatra Cabuz ,  Max C. Glenn ,  Francis M. Erdmann ,  Robert D. Horning

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/308 ,  H01L29/84 ,  B32B9/00

CPC classification number: B81C1/00365 ,  B81C2201/0164 ,  Y10T428/21 ,  Y10T428/2495

Abstract: Layers of boron-doped silicon having reduced out-of-plane curvature are disclosed. The layers have substantially equal concentrations of boron near the top and bottom surfaces. Since the opposing concentrations are substantially equal, the compressive stresses on the layers are substantially balanced, thereby resulting in layers with reduced out-of-plane curvature.

Abstract translation: 公开了具有减小的平面外曲率的硼掺杂硅层。 这些层在顶部和底部表面附近具有基本相等的硼浓度。 由于相反的浓度基本相等，所以层上的压缩应力基本平衡，从而导致具有减小的面外曲率的层。

公开(公告)号：US20040253760A1

公开(公告)日：2004-12-16

申请号：US10462310

申请日：2003-06-13

Applicant: Agency For Science, Technology And Research

Inventor： Qingxin Zhang ,  Zhe Wang

IPC: H01L021/00

CPC classification number: B81C1/00666 ,  B81B2201/0257 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81C2201/0164 ,  H04R31/003

Abstract: A method of fabricating a highly perforated silicon diaphragm is described. A single crystal silicon substrate of a first conductivity type is provided. First ions of a second conductivity type opposite the first conductivity type are implanted into the single crystal silicon substrate to form an etch stop layer. Second ions of the first conductivity type are selectively implanted into the single crystal silicon substrate to form a pattern of holes in a portion of the substrate. Third ions of the first conductivity type are implanted overlying the pattern of holes and forming a first ohmic contact region. Fourth ions of the second conductivity type are implanted into the substrate not surrounding the pattern of holes to form a second ohmic contact region. A nitride layer is deposited on a frontside and a backside of the silicon substrate. Contacts are formed through the nitride layer to the first and second ohmic contact regions. Thereafter, the backside nitride layer is patterned and from the backside, the silicon substrate not covered by the nitride layer is etched away to the etch stop layer and, simultaneously, the pattern of holes is selectively etched away to complete formation of a perforated diaphragm.

Abstract translation: 描述了制造高度穿孔的硅膜的方法。 提供了第一导电类型的单晶硅衬底。 与第一导电类型相反的第二导电类型的第一离子注入到单晶硅衬底中以形成蚀刻停止层。 第一导电类型的第二离子被选择性地注入到单晶硅衬底中以在衬底的一部分中形成孔的图案。 将第一导电类型的第三离子注入覆盖孔的图案并形成第一欧姆接触区域。 将第二导电类型的第四离子注入到不围绕孔图案的衬底中以形成第二欧姆接触区域。 氮化物层沉积在硅衬底的前侧和背面。 触头通过氮化物层形成到第一和第二欧姆接触区域。 此后，将背面氮化物层图案化，并且从背面，未被氮化物层覆盖的硅衬底被蚀刻掉到蚀刻停止层，并且同时，孔的图案被选择性地蚀刻掉以完成多孔隔膜的形成。

公开(公告)号：US20040157426A1

公开(公告)日：2004-08-12

申请号：US10410158

申请日：2003-04-10

Inventor： Luc Ouellet ,  Robert Antaki

IPC: H01L021/8242

CPC classification number: B81C1/00246 ,  B81C1/00666 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0169 ,  B81C2203/0735

Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.

Abstract translation: 通过在公共衬底上制造包括多个电子部件的电子器件，在公共衬底上制造微电子机械（MEM）器件和电子器件，在电子器件上沉积热稳定的互连层，封装互连 具有保护层的电子器件，在保护层上形成牺牲层，牺牲层中的开孔和保护层，以允许MEM器件与电子器件的连接，通过沉积和图案化制造MEM器件至少一个 非晶硅层，并且去除牺牲层的至少一部分。 以这种方式，MEM装置可以在同一基板上的电子装置之后制造。