公开(公告)号：US07091545B2

公开(公告)日：2006-08-15

申请号：US11017346

申请日：2004-12-20

Applicant: Tieh Chiang Wu ,  Chien-Chang Huang ,  Chin-Ling Huang ,  Bo Ching Jiang ,  Yu-Wei Ting

Inventor： Tieh Chiang Wu ,  Chien-Chang Huang ,  Chin-Ling Huang ,  Bo Ching Jiang ,  Yu-Wei Ting

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/0207 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876

Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.

Abstract translation: 一种存储器件及其制造方法。 在本发明的存储器件中，衬底具有多个深沟槽，其中形成在相邻行中的深沟槽交错。 深沟槽电容器和控制栅极依次设置在每个深沟槽中。 字线分别设置在控制栅上，并且每条字线电耦合到其下的控制栅极。 扩散区域设置在衬底中并分别围绕深沟槽以用作垂直晶体管的源。 每个扩散区电连接到周围的深沟槽电容器。 活动区分别沿着第二方向设置在控制门的行上。 每个有效区域与控制门重叠的区域具有至少一个缩进。

公开(公告)号：US20050104109A1

公开(公告)日：2005-05-19

申请号：US11017346

申请日：2004-12-20

Applicant: Tieh Wu ,  Chien-Chang Huang ,  Chin-Ling Huang ,  Bo Ching Jiang ,  Yu-Wei Ting

Inventor： Tieh Wu ,  Chien-Chang Huang ,  Chin-Ling Huang ,  Bo Ching Jiang ,  Yu-Wei Ting

IPC: D02G3/00 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876

Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.

Abstract translation: 一种存储器件及其制造方法。 在本发明的存储器件中，衬底具有多个深沟槽，其中形成在相邻行中的深沟槽交错。 深沟槽电容器和控制栅极依次设置在每个深沟槽中。 字线分别设置在控制栅上，并且每条字线电耦合到其下的控制栅极。 扩散区域设置在衬底中并分别围绕深沟槽以用作垂直晶体管的源。 每个扩散区电连接到周围的深沟槽电容器。 活动区分别沿着第二方向设置在控制门的行上。 每个有效区域与控制门重叠的区域具有至少一个缩进。

公开(公告)号：US06844207B2

公开(公告)日：2005-01-18

申请号：US10452179

申请日：2003-06-02

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang ,  Chin-Ling Huang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang ,  Chin-Ling Huang

IPC: G11C29/02 ,  H01L31/26 ,  H01L21/66

CPC classification number: G11C29/50008 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025

Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.

Abstract translation: 用于检测DRAM装置中位线接触和有源区的对准是否正常的方法及其测试装置。 在本发明中，在存储区域中形成多个存储单元，同时在划线区域中形成至少一个测试装置。 第一电阻和第二电阻由测试装置检测。 根据第一电阻和第二电阻确定测试装置的位线和条形有源区域的正常对准。 最后，根据测试装置的位线接触和条形有源区域的对准是否正常来确定位线触点的对齐和存储区域中的有效区域是否正常。

公开(公告)号：US20050002221A1

公开(公告)日：2005-01-06

申请号：US10902450

申请日：2004-07-29

Applicant: Tie Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Jiang

Inventor： Tie Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Jiang

IPC: G11C8/14 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02 ,  G11C11/24

CPC classification number: H01L27/10861 ,  G11C8/14 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10891

Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

Abstract translation: 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。

公开(公告)号：US06825053B2

公开(公告)日：2004-11-30

申请号：US10601386

申请日：2003-06-23

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang

IPC: H01L2166

CPC classification number: H01L27/10861 ,  G11C8/14 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10891

Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

Abstract translation: 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。

公开(公告)号：US07217581B2

公开(公告)日：2007-05-15

申请号：US11339687

申请日：2006-01-26

Applicant: Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

Inventor： Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

IPC: H01L21/00

CPC classification number: G03F9/7088 ,  G03F7/70633 ,  G03F7/70658 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract translation: 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。

公开(公告)号：US06946678B2

公开(公告)日：2005-09-20

申请号：US10902450

申请日：2004-07-29

Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang

Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Ching Jiang

IPC: G11C8/14 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02 ,  H01L23/58

CPC classification number: H01L27/10861 ,  G11C8/14 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10891

Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

Abstract translation: 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。

公开(公告)号：US20050184289A1

公开(公告)日：2005-08-25

申请号：US11096836

申请日：2005-03-30

Applicant: Tie Wu ,  Chien-Chang Huang ,  Bo Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

Inventor： Tie Wu ,  Chien-Chang Huang ,  Bo Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

IPC: G11C29/36 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L21/66 ,  H01L23/58 ,  H01L29/10

CPC classification number: H01L27/10876 ,  G11C11/401 ,  G11C29/36 ,  G11C2029/5002 ,  H01L22/34 ,  H01L27/10841

Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

Abstract translation: 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。

公开(公告)号：US06838296B2

公开(公告)日：2005-01-04

申请号：US10448920

申请日：2003-05-29

Applicant: Tie-Jiang Wu ,  Chien-Chang Huang ,  Bo-Ching Jiang ,  Yu-Wei Ting

Inventor： Tie-Jiang Wu ,  Chien-Chang Huang ,  Bo-Ching Jiang ,  Yu-Wei Ting

IPC: H01L21/8242 ,  H01L23/544 ,  H01L27/02 ,  H01L21/66

CPC classification number: H01L27/10861 ,  G11C11/401 ,  G11C2029/5002 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/10867 ,  H01L27/1087

Abstract: A test device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices. A quadrilateral active area is disposed in the scribe line region, with four equilaterals and four vertex angles. Parallel first and second deep trench capacitors are disposed in the quadrilateral active area. The first deep trench capacitor has a first surface aligned with a second surface of the second deep trench capacitor. The first and second vertex angles of the four vertex angles have a diagonal line essentially perpendicular to the first and second surfaces. The first and second vertex angles are a predetermined distance from the first surface and the second surface respectively.

Abstract translation: 用于检测DRAM器件中深沟槽电容器和有源区域的对准的测试装置和方法。 四边形有源区域设置在划线区域，具有四个平衡和四个顶角。 平行的第一和第二深沟槽电容器设置在四边形有源区域中。 第一深沟槽电容器具有与第二深沟槽电容器的第二表面对准的第一表面。 四个顶角的第一和第二顶角具有基本上垂直于第一和第二表面的对角线。 第一和第二顶角分别与第一表面和第二表面预定的距离。