公开(公告)号：US11004833B1

公开(公告)日：2021-05-11

申请号：US16792560

申请日：2020-02-17

Applicant: XILINX, INC.

Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni ,  Sundeep Ram Gopal Agarwal

IPC: H01L25/065 ,  H01L23/48

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.

公开(公告)号：US10411710B1

公开(公告)日：2019-09-10

申请号：US16211149

申请日：2018-12-05

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Sree RKC Saraswatula ,  Jing Jing Chen ,  Teja Masina ,  Narendra Kumar Pulipati ,  Santosh Yachareni

IPC: H03K19/177

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

公开(公告)号：US10396799B1

公开(公告)日：2019-08-27

申请号：US15839462

申请日：2017-12-12

Applicant: Xilinx, Inc.

Inventor： Vishwak R Manda ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou ,  Jing Jing Chen ,  Michael Tsivyan

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/0185

Abstract: A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.

公开(公告)号：US09509307B1

公开(公告)日：2016-11-29

申请号：US14492370

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Vikram Santurkar ,  Anil Kumar Kandala ,  Santosh Yachareni ,  Shidong Zhou ,  Robert Fu ,  Philip Costello ,  Sandeep Vundavalli ,  Steven P. Young ,  Brian C. Gaide

IPC: H03K19/003 ,  H03K19/173 ,  H03K19/00 ,  G11C7/12

CPC classification number: H03K19/003 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/417 ,  H03K19/0008 ,  H03K19/1737

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract translation: 互连多路复用器包括第一多路复用器级的多个CMOS通过门，其耦合以接收由互连多路复用器输出的数据; 输出反相器，其耦合到所述多个CMOS遍栅的输出，其中所述输出反相器的输出是所述互连多路复用器的输出; 以及耦合到所述多个CMOS通孔的多个存储元件; 其中在启动模式期间将多个CMOS通孔的输入拉至公共电位。 还公开了降低集成电路中的争用电流的方法。