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21.
公开(公告)号:US20190196277A1
公开(公告)日:2019-06-27
申请号:US14907911
申请日:2015-12-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor: Yuejun TANG , Yafeng LI
IPC: G02F1/1343 , G02F1/1335
CPC classification number: G02F1/134336 , G02F1/1333 , G02F1/133512 , G02F1/1339
Abstract: Disclosed is an array substrate and a method for manufacturing the same, a liquid crystal display panel, wherein the array substrate includes: a first material layer and a first conductive layer formed on the first material layer, wherein a region of the first material layer that is not covered by the first conductive layer is etched away in whole or in part along a thickness direction. The array substrate can enable an effective gap of a liquid crystal cell to be increased, thereby improving the transmittance of the panel, and meanwhile can ensure that the response time of the liquid crystal display panel containing the array substrate will not be increased.
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公开(公告)号:US20180338121A1
公开(公告)日:2018-11-22
申请号:US15327301
申请日:2016-12-30
Inventor: Yafeng LI
IPC: H04N9/30
Abstract: Disclosed is a gate driving circuit and a display device, which solve the technical problem that the prior art is easy to cause abnormal output of gate driving signals. The gate driving circuit includes a precharge unit circuit, an output unit circuit, and a holding unit circuit. The output unit circuit includes a first reference point and a clock signal line. The holding unit circuit includes a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line
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公开(公告)号:US20180114498A1
公开(公告)日:2018-04-26
申请号:US15308843
申请日:2016-06-13
Inventor: Yafeng LI
IPC: G09G3/36 , G02F1/1345
CPC classification number: G09G3/3677 , G02F1/13454 , G02F1/136286 , G02F1/1368 , G02F2202/104 , G09G2310/0283 , G09G2310/0286 , H01L27/1222 , H01L27/124 , H01L27/1255
Abstract: A GOA electric circuit introduces a resistor and a timing signal, which are used to replace a second capacitor in the existing skills. One terminal of the resistor is connected to a constant high voltage level and the other terminal thereof is connected to a gate electrode of a ninth thin-film transistor. A source electrode of the ninth thin-film transistor is electrically connected to the timing signal. In the stage maintaining the output terminal at low voltage level, the voltage level of the second node can be changed between high and low voltage levels as the timing signal is changed, and the voltage level of the second node is pulled down in a specific frequency. This effectively prevents the second node from being at high voltage level for a long time and avoids the problem of threshold voltage shifting, and therefore improves the stability of GOA electric circuit.
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24.
公开(公告)号:US20180061346A1
公开(公告)日:2018-03-01
申请号:US14916343
申请日:2016-02-24
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2310/0243 , G09G2310/0286 , G09G2310/0289 , G09G2310/08
Abstract: A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.
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公开(公告)号:US20170255065A1
公开(公告)日:2017-09-07
申请号:US14907865
申请日:2016-01-12
Inventor: Yafeng LI , Xiangyi PENG
IPC: G02F1/1343
CPC classification number: G02F1/134309 , G02F1/134363 , G02F1/13439 , G02F2001/134372 , G02F2201/121 , G02F2201/123 , G02F2201/50
Abstract: A liquid crystal panel and a pixel structure thereof are described. The pixel structure has a common electrode, a protecting layer, a plurality of pixel electrodes, and a plurality of first channels. The protecting layer is located on the common electrode; the pixel electrodes are located on the protecting layer; and the first channels are located between the neighboring pixel electrodes and pass through the protecting layer, so that the first channels expose a top surface of the common electrode.
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