公开(公告)号：US10269664B2

公开(公告)日：2019-04-23

申请号：US15782161

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jia-Ming Lin ,  Wei-Ken Lin ,  Shiu-Ko JangJian ,  Chun-Che Lin

IPC: H01L21/66 ,  H01L21/3115 ,  H01L21/762 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.