公开(公告)号：US11088020B2

公开(公告)日：2021-08-10

申请号：US15691035

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Li-Lin Su ,  Shin-Yi Yang ,  Cheng-Chi Chuang ,  Hsin-Ping Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.

公开(公告)号：US10804143B2

公开(公告)日：2020-10-13

申请号：US16458399

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer, an etching stop layer, a barrier layer, a conductive layer, and a second dielectric layer. The first dielectric layer is over the integrated circuit. The etching stop layer is over the first dielectric layer. The barrier layer has an upper portion extending along a top surface of the etching stop layer and a lower portion extending downwardly from the upper portion along a sidewall of the etching stop layer and a sidewall of the first dielectric layer. The conductive layer is over the barrier layer and having a void region extending through the conductive layer, the barrier layer and the etching stop layer. The second dielectric layer is over the conductive layer and the void region.

公开(公告)号：US10714421B2

公开(公告)日：2020-07-14

申请号：US15689784

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Yung-Hsu Wu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

公开(公告)号：US10535560B2

公开(公告)日：2020-01-14

申请号：US15652901

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L23/522

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

公开(公告)号：US10534273B2

公开(公告)日：2020-01-14

申请号：US15586881

申请日：2017-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US10340181B2

公开(公告)日：2019-07-02

申请号：US15353850

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528

Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

公开(公告)号：US10276396B2

公开(公告)日：2019-04-30

申请号：US15668216

申请日：2017-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Chia-Tien Wu ,  Wei-Chen Chu

IPC: H01L21/48 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3213

Abstract: A method for forming a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate and forming an etch stop layer with a hole over the first dielectric layer. The method also includes forming a second dielectric layer over the etch stop layer and forming a first mask element with a trench opening over the second dielectric layer. The method further includes forming a second mask element over the first mask element, and the second mask element has a via opening. In addition, the method includes etching the second dielectric layer through the via opening and etching the second dielectric layer through the trench opening. As a result, a trench and a via hole are formed in the second dielectric layer and the first dielectric layer, respectively. The method includes forming a conductive material in the via hole and the trench.

公开(公告)号：US10269715B2

公开(公告)日：2019-04-23

申请号：US16022131

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Wei-Chen Chu

IPC: H01L21/44 ,  H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

公开(公告)号：US10163690B2

公开(公告)日：2018-12-25

申请号：US15389060

申请日：2016-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Wei-Chen Chu

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311

Abstract: Two-dimensional (2-D) interconnects in a one-dimensional (1-D) patterning layout for integrated circuits is disclosed. This disclosure provides methods of connecting even or odd numbered lines that are in the x-direction of a 1-D patterning layout through 2-D interconnects in the y-direction. Depending on device design needs, 2-D interconnects may be perpendicular or non-perpendicular to the even or odd numbered lines. The freedom of two-dimensional patterning compared to conventional self-aligned multiple patterning (SAMP) processes used in the 1-D patterning processes is provided. The two-dimensional patterning described herein provides line widths that match the critical dimensions in both x and y directions. The separation between the 1-D lines or between 2-D interconnects and the end of 1-D lines can be kept to a constant and at a minimum.