公开(公告)号：US20180342459A1

公开(公告)日：2018-11-29

申请号：US15605987

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A method of forming an interconnection structure includes forming a dielectric structure over a non-insulator structure; forming a hole in the dielectric structure to expose the non-insulator structure; forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process; forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process; and forming a metal over the second diffusion barrier layer.

公开(公告)号：US20230223334A1

公开(公告)日：2023-07-13

申请号：US18173283

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/7684 ,  H01L21/76832 ,  H01L21/76802 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53276 ,  H01L21/768 ,  H01L21/76852 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53252

Abstract: A interconnect structure includes a lower metal, a dielectric layer, an upper metal, and a graphene layer. The dielectric layer laterally surrounds the lower metal. The upper metal is over the lower metal. The graphene layer is over a top surface of the upper metal and opposite side surfaces of the upper metal from a cross-sectional view.

公开(公告)号：US20220384336A1

公开(公告)日：2022-12-01

申请号：US17884301

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

公开(公告)号：US20190157144A1

公开(公告)日：2019-05-23

申请号：US15820419

申请日：2017-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shih-Kang FU ,  Meng-Pei LU ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/321 ,  H01L23/532

Abstract: A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.

公开(公告)号：US20170317010A1

公开(公告)日：2017-11-02

申请号：US15651834

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/373 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/3736 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/53276

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.