公开(公告)号：US6049225A

公开(公告)日：2000-04-11

申请号：US23369

申请日：1998-02-13

Applicant: Joseph Huang ,  Richard G. Cliff ,  Srinivas T. Reddy

Inventor： Joseph Huang ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output pins of the device. While the techniques shown greatly increase circuit flexibility, they avoid the unnecessary overhead of interconnectivity which is completely general.

Abstract translation: 在可编程逻辑阵列集成电路器件中，使用各种技术来增加器件的核心逻辑可以连接到器件的输入和/或输出引脚的灵活性。 虽然显示的技术大大增加了电路灵活性，但它们避免了完全一般的不必要的互连开销。

公开(公告)号：US5963049A

公开(公告)日：1999-10-05

申请号：US807561

申请日：1997-02-28

Applicant: Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

Inventor： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

Abstract: A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

公开(公告)号：US5847617A

公开(公告)日：1998-12-08

申请号：US909337

申请日：1997-08-11

Applicant: Srinivas T. Reddy ,  David Edward Jefferson ,  Richard G. Cliff ,  Cameron McClintock

Inventor： Srinivas T. Reddy ,  David Edward Jefferson ,  Richard G. Cliff ,  Cameron McClintock

IPC: H03K3/03 ,  H03L7/099 ,  H03B5/24

CPC classification number: H03L7/0997 ,  H03K3/0315

Abstract: A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.

Abstract translation: 提供了可变路径长度的压控振荡器电路。 振荡器电路具有由一系列压控逆变器级形成的环形振荡器。 基于存储在存储器中的路径长度配置数据来选择环路的路径长度（即，逆变器级数）。 所选择的路径长度决定了环形振荡器的额定或中心频率。 通过改变环形振荡器路径中每个反相器级的延迟，振荡器电路的输出频率就关于该中心频率进行电压调谐。 可以使用各种类型的压控变频器级，包括电流欠压级，可变容性负载逆变级和差分延迟逆变级。 压控振荡器电路可用于可编程逻辑器件上的锁相环，用于频率合成或消除时钟偏移。

公开(公告)号：US20110204919A1

公开(公告)日：2011-08-25

申请号：US13098450

申请日：2011-04-30

Applicant: Andy L. Lee ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Richard G. Cliff ,  Cameron R. McClintock ,  Srinivas T. Reddy ,  David Lewis

Inventor： Andy L. Lee ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Richard G. Cliff ,  Cameron R. McClintock ,  Srinivas T. Reddy ,  David Lewis

IPC: H03K19/177

CPC classification number: H03K19/17784 ,  H03K19/17788 ,  H03K19/17792

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

公开(公告)号：US07936184B2

公开(公告)日：2011-05-03

申请号：US11361642

申请日：2006-02-24

Applicant: Andy L. Lee ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Richard G. Cliff ,  Cameron R. McClintock ,  Srinivas T. Reddy ,  David Lewis

Inventor： Andy L. Lee ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Richard G. Cliff ,  Cameron R. McClintock ,  Srinivas T. Reddy ,  David Lewis

IPC: H01L25/00

CPC classification number: H03K19/17784 ,  H03K19/17788 ,  H03K19/17792

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract translation: 可编程逻辑器件（PLD）至少包括两个区域。 每个区域包括具有一组晶体管的电路。 两个区域中的每一个具有对应的固定晶体管阈值电压，对应的固定晶体管体偏置和相应的固定电源电压。

公开(公告)号：US07236008B1

公开(公告)日：2007-06-26

申请号：US11611122

申请日：2006-12-14

Applicant: Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

Inventor： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

IPC: G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17728

Abstract: Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

Abstract translation: 提供具有多种尺寸的存储器的集成电路的电路，方法和装置。 存储器可以是专用的嵌入式存储器，或者它们可以是使用逻辑元件或其他适当电路中的存储器或查找表形成的分布式存储器。 用于分布式存储器的逻辑元件不需要的配置位也可以用于数据存储。 这些各种存储器可以以不同的组合组合或以其他方式链接或链接在一起以形成不同大小的较大存储器。

公开(公告)号：US06480028B2

公开(公告)日：2002-11-12

申请号：US10062741

申请日：2002-02-01

Applicant: David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pederson ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

Inventor： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pederson ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC: H03K19177

CPC classification number: H03K19/1776 ,  H03K19/17736

Abstract: A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

Abstract translation: 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在更高长度的超超区域互连资源 装置。

公开(公告)号：US06462577B1

公开(公告)日：2002-10-08

申请号：US09761608

申请日：2001-01-16

Applicant: Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Brian D. Johnson ,  Ketan H. Zaveri ,  Mario Guzman ,  Quyen Doan

Inventor： Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Brian D. Johnson ,  Ketan H. Zaveri ,  Mario Guzman ,  Quyen Doan

IPC: H03K19177

CPC classification number: H03K19/1776 ,  G11C8/12 ,  H03K19/17728

Abstract: A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.

Abstract translation: 提供了一种可编程逻辑器件，其中可编程地将逻辑阵列块（LAB）配置为用作各种存储器结构之一。 可配置的存储器结构可以具有单独的读和写地址，从而使得可以实现各种存储器结构，例如FIFO存储器，ROM，RAM和移位寄存器。

公开(公告)号：US06373280B1

公开(公告)日：2002-04-16

申请号：US09795796

申请日：2001-02-28

Applicant: Christopher F. Lane ,  Srinivas T. Reddy

Inventor： Christopher F. Lane ,  Srinivas T. Reddy

IPC: A03K19177

CPC classification number: H03K19/17736 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.

Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。 在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。 快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。 一些主导体可以携带离开设备的信号。 其他主导体可以携带在设备上产生的信号。 网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。 提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。

公开(公告)号：US06351152B1

公开(公告)日：2002-02-26

申请号：US09401743

申请日：1999-09-23

Applicant: Srinivas T. Reddy ,  Anil Gupta

Inventor： Srinivas T. Reddy ,  Anil Gupta

IPC: H03K1762

CPC classification number: H03K17/693 ,  H03K17/005

Abstract: A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

Abstract translation: 用MOS晶体管实现的查找表电路，其使用组合逻辑来产生使晶体管能够实现的信号。 公开了使用16个输入和4个选择线的电路。 选择线中的两条被用作组合逻辑的输入，包括四个或非门以产生电路第三级晶体管的使能信号。 这导致信号从输入到查找表电路的输出的传播延迟的减小。