公开(公告)号：US12211423B2

公开(公告)日：2025-01-28

申请号：US18391087

申请日：2023-12-20

Applicant: Samsung Display Co., LTD.

Inventor： Danwon Lim ,  Hyunjoon Kim ,  Jaeyong Jang ,  Bon-Yong Koo

IPC: G09G3/20 ,  G09G3/3233

Abstract: A display panel includes: sub-pixels each including a storage capacitor configured to have a data voltage written thereto; a capacitor node line connected to the storage capacitor of at least one of the sub-pixels; a compensation reference voltage line configured to receive a compensation reference voltage; a first power supply voltage line configured to receive a first power supply voltage; a first connection transistor configured to connect the compensation reference voltage line to the capacitor node line based on an emission signal; and a second connection transistor configured to connect the first power supply voltage line to the capacitor node line based on the emission signal.

公开(公告)号：US10468534B2

公开(公告)日：2019-11-05

申请号：US15866309

申请日：2018-01-09

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong Koo ,  Jung-Hun Noh ,  Sun Kwang Kim ,  Yeon Kyung Kim

IPC: H01L29/786 ,  H01L29/49 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A transistor array panel according to an exemplary embodiment includes a substrate, and a first transistor and a second transistor positioned on the substrate. Each of the first transistor and the second transistor includes: a first electrode; a second electrode overlapping the first electrode; a spacing member positioned between the first electrode and the second electrode; a semiconductor layer extending along a side wall of the spacing member; and a gate electrode overlapping the semiconductor layer. A thickness of the spacing member of the first transistor is larger than a thickness of the spacing member of the second transistor.

公开(公告)号：US09153599B2

公开(公告)日：2015-10-06

申请号：US14322366

申请日：2014-07-02

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong Koo ,  Jeong Min Park ,  Ho-Kyoon Kwon ,  Yun Hee Kwak

IPC: H01L29/84 ,  H01L27/12 ,  G02F1/1345 ,  G02F1/1362

CPC classification number: H01L27/1214 ,  G02F1/13458 ,  G02F1/136227 ,  H01L27/124

Abstract: A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.

Abstract translation: 薄膜晶体管阵列面板包括栅极线和形成有相同层材料的驱动器连接线，形成有相同层材料的数据线和驱动焊盘，第一场产生电极和形成有相同层的连接构件 材料和形成有相同层材料的第二场产生电极和虚拟电极层。

公开(公告)号：US08624243B2

公开(公告)日：2014-01-07

申请号：US13918060

申请日：2013-06-14

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong Koo ,  Kyung-Wook Kim

IPC: H01L23/58

CPC classification number: H01L27/105 ,  G02F1/1309 ,  G02F1/1345 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.