公开(公告)号：US11948882B2

公开(公告)日：2024-04-02

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53266

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20230230915A1

公开(公告)日：2023-07-20

申请号：US18127342

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/82 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/5222 ,  H01L23/3185 ,  H01L24/05 ,  H01L23/5283 ,  H01L23/481 ,  H01L23/53295 ,  H01L21/76832 ,  H01L23/485 ,  H01L23/5226 ,  H01L21/82 ,  H01L21/561 ,  H01L21/78 ,  H01L23/562 ,  H01L2224/0237 ,  H01L2224/024

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US11670559B2

公开(公告)日：2023-06-06

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Jung-Hoon Han ,  Jiho Kim ,  Young-Yong Byun ,  Yeonjin Lee ,  Jihoon Chang

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L23/58 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L21/78 ,  H01L23/291 ,  H01L23/296 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02181 ,  H01L2224/05541 ,  H01L2224/05553

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US11495533B2

公开(公告)日：2022-11-08

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US11342235B2

公开(公告)日：2022-05-24

申请号：US16898943

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Junyong Noh ,  Yeonjin Lee ,  Junghoon Han

IPC: H01L21/78 ,  H01L21/66

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.