公开(公告)号：US08996964B2

公开(公告)日：2015-03-31

申请号：US13786509

申请日：2013-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghyeog Choi ,  Junjin Kong ,  Hong Rak Son ,  Pilsang Yoon

IPC: H03M13/00 ,  H03M13/37 ,  H03M13/45

CPC classification number: H03M13/3784 ,  H03M13/3707 ,  H03M13/45

Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.

Abstract translation: 存储装置包括包括多个存储器单元的非易失性存储器件，以及错误校正电路，被配置为从非易失性存储器件接收主数据和辅助数据，并对主数据进行硬判决解码操作，并进一步被配置为执行 基于次要数据对主数据进行软判决解码操作。 在硬判决读取操作中从多个存储器单元中读取主数据，并且从主数据中从被编程到特定状态的存储器单元读取次数据。